Verilog Coding for Logic Synthesis

Table Of Examples

Example 3.1: Verilog Code Using Wire Declaration

Example 3.2: Verilog Code Using Wire Declaration for a 4 Bit Bus

Example 3.3: Verilog Code Using Reg Declaration

Example 3.4: Verilog Code Using Reg Declaration for a 8 Bit Bus

Example 3.5: Verilog Code Showing a Tri Declaration

Example 3.6: Verilog Code Using Strength Assignment

Example 3.7: Example Showing Syntax Defining a UDP

Example 3.8: Verilog Example for Defining a UDP Primitive and Instantiating the Primitive

Example 3.9: Verilog Example for Defining a Sequential UDP Primitive and Instantiating the Primitive

Example 3.10: Verilog Example for Defining a Positive Edge Sequential UDP Primitive and Instantiating the Primitive

Example 4.1: Verilog Example of Module A, Module B and Fullchip Interconnect

Example 4.2: Verilog Code for the Design of Figure 4.4

Example 4.3: Verilog Code for Gated Clock Design Using BOOLEAN Assignment

Example 4.4: Verilog Code for Gated Clock Design Using Gate Instantiation

Example 4.5: Verilog Code for Gated Clock Design Using Gate Instantiation to Drive 32 Flip-flops

Example 4.6: Verilog Code for an Asynchronous Reset Design

Example 4.7: Verilog Code for a Synchronous Reset Design

Example 4.8: Verilog Code Showing Usage of Non-blocking Statement

Example 4.9: Verilog Code for Example 4.8 with the Output Assignment Re-arranged

Example 4.10: Verilog Code for Example 4.9 with the Output Assignment Re-arranged

Example 4.11: Verilog Code for Testbench for Simulation of Examples 4.8, 4.9 ...