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Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition by Samir Palnitkar

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Appendix D. Formal Syntax Definition

This appendix contains the formal definition[1] of the Verilog-2001 standard in Backus-Naur Form (BNF). The formal definition contains a description of every possible usage of Verilog HDL. Therefore, it is very useful if there is a doubt on the usage of certain Verilog HDL syntax.

Though the BNF may be hard to understand initially, the following summary may help the reader better understand the formal syntax definition:

  1. Bold text represents literal words themselves (these are called terminals). Example: module.

  2. Non-bold text (possibly with underscores) represents syntactic categories (these are called non terminals). Example: port_identifier.

  3. Syntactic categories are defined using the form: syntactic_category ::= ...

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