Before we discuss the details of the Verilog language, we must first understand basic hierarchical modeling concepts in digital design. The designer must use a “good” design methodology to do efficient Verilog HDL-based design. In this chapter, we discuss typical design methodologies and illustrate how these concepts are translated to Verilog. A digital simulation is made up of various components. We talk about the components and their interconnections.
Understand top-down and bottom-up design methodologies for digital design.
Explain differences between modules and module instances in Verilog.
Describe four levels of abstraction—behavioral, data flow, gate level, and switch level—to represent ...