In the previous chapters, we acquired an understanding of the fundamental hierarchical modeling concepts, basic conventions, and Verilog constructs. In this chapter, we take a closer look at modules and ports from the Verilog language point of view.
Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
Understand how to define the port list for a module and declare it in Verilog.
Describe the port connection rules in a module instantiation.
Understand how to connect ports to external signals, by ordered list, and by name.
Explain hierarchical ...