We learned the basic features of Verilog in the preceding chapters. In this chapter. we will discuss additional features that enhance the Verilog language, making it powerful and flexible for modeling and analyzing a design.
Describe procedural continuous assignment statements
release. Explain their significance in modeling and debugging.
Understand how to override parameters by using the
defparam statement at the time of module instantiation.
Explain conditional compilation and execution of parts of the Verilog description.
Identify system tasks for file output, displaying hierarchy, strobing, random number generation, memory initialization, and value change dump ...