book

Verilog HDL Design Examples

Name: Verilog HDL Design Examples
Author: Joseph Cavanagh
ISBN: 9781351596299

by Joseph Cavanagh

October 2017

Intermediate to advanced

673 pages

13h 59m

English

CRC Press

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Cover
Halftitle Page
Title Page
Copyright
Table of Contents
Preface
Chapter 1 Introduction to Logic Design Using Verilog HDL
1.1 Logic Elements1.1.1 Comments1.1.2 Logic Gates1.1.3 Logic Macro Functions1.1.4 Procedural Flow Control1.1.5 Net Data Types1.1.6 Register Data Types1.2 Expressions1.2.1 Operands1.2.2 Operators1.3 Modules and Ports1.3.1 Designing a Test Bench for Simulation1.4 Built-In Primitives1.4.1 Built-In Primitive Design Examples1.5 User-Defined Primitives1.5.1 Defining a User-Defined Primitive1.5.2 Combinational User-Defined Primitives1.5.3 Sequential User-Defined Primitives1.6 Dataflow Modeling1.6.1 Continuous Assignment1.6.2 Reduction Operators1.6.3 Conditional Operator1.6.4 Relational Operators1.6.5 Logical Operators1.6.6 Bitwise Operators1.6.7 Shift Operators
1.7 Behavioral Modeling
1.7.1 Initial Statement1.7.2 Always Statement1.7.3 Intrastatement Delay1.7.4 Interstatement Delay1.7.5 Blocking Assignments1.7.6 Nonblocking Assignments1.7.7 Conditional Statements1.7.8 Case Statement1.7.9 Loop Statements1.7.10 Logical, Algebraic, and Rotate Shift Operations1.8 Structural Modeling1.8.1 Module Instantiation1.8.2 Ports1.8.3 Design Examples1.9 Tasks and Functions1.9.1 Task Declaration1.9.2 Task Invocation1.9.3 Function Declaration1.9.4 Function Invocation1.10 Problems
Chapter 2 Combinational Logic Design Using Verilog HDL
2.1 Number Systems2.1.1 Binary Number System2.1.2 Octal Number System2.1.3 Decimal Number System2.1.4 Hexadecimal Number System2.2 Boolean Algebra2.2.1 Axioms2.2.2 Theorems2.2.3 Other Terms for Boolean Algebra2.3 Logic Equations2.4 Multiplexers2.5 Comparators2.6 Programmable Logic Devices2.6.1 Programmable Read-Only Memories2.6.2 Programmable Array Logic2.6.3 Programmable Logic Array2.7 Additional Design Examples2.8 Problems
Chapter 3 Sequential Logic Design Using Verilog HDL
3.1 Introduction3.1.1 Definition of a Sequential Machine3.2 Synchronous Sequential Machines3.2.1 Synthesis Procedure3.2.2 Equivalent States3.2.4 Mealy Machines3.2.5 Synchronous Registers3.2.6 Synchronous Counters3.3 Asynchronous Sequential Machines3.3.1 Synthesis Procedure3.3.2 Hazards3.3.3 Oscillations3.3.4 Races3.3.5 Design Examples of Asynchronous Sequential Machines3.4 Pulse-Mode Asynchronous Sequential Machines3.4.1 Synthesis Procedure3.4.2 SR Latches with D Flip-Flops as Storage Elements3.4.3 T Flip-Flops as Storage Elements3.5 Problems

Chapter 4 Computer Arithmetic Design Using Verilog HDL
4.1 Introduction4.2 Fixed-Point Addition4.2.1 Full Adder4.2.2 Three-Bit Adder4.2.3 Four-Bit Ripple-Carry Adder4.2.4 Carry Lookahead Adder4.3 Fixed-Point Subtraction4.3.1 Four-Bit Ripple Subtractor4.3.2 Eight-Bit Subtractor4.3.3 Four-Bit Dataflow Adder/Subtractor4.3.4 Eight-Bit Behavioral Adder/Subtractor4.4 Fixed-Point Multiplication4.4.1 Behavioral Four-Bit Multiplier4.4.2 Three-Bit Array Multiplier4.4.3 Four-Bit Dataflow Multiplication Using the Multiply Operator4.5 Fixed-Point Division4.6 Arithmetic and Logic Unit4.7 Decimal Addition4.7.1 Decimal Addition with Sum Correction4.7.2 Decimal Addition Using Multiplexers for Sum Correction4.8 Decimal Subtraction4.8.1 Decimal Subtraction Using Full Adders and Built-In Primitives for Four Bits4.8.2 Decimal/Binary Subtraction Using Full Adders and Built-In Primitives for Eight Bits4.8.3 Eight-Bit Decimal Subtraction Unit with Built-In Primitives and Full Adders Designed Using Behavioral Modeling4.9 Decimal Multiplication4.10 Decimal Division4.11 Floating-Point Addition4.12 Floating-Point Subtraction4.12.1 True Addition and True Subtraction4.13 Floating-Point Multiplication4.14 Floating-Point Division4.15 Problems
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems
Index

Content preview from Verilog HDL Design Examples

Event management in Verilog hardware description language (HDL) is controlled by an event queue. Verilog modules generate events in the test bench, which provide stimulus to the module under test. These events can then produce new events by the modules under test. Since the Verilog HDL Language Reference Manual (LRM) does not specify a method of handling events, the simulator must provide a way to arrange and schedule these events in order to accurately model delays and obtain the correct order of execution. The manner of implementing the event queue is vendor-dependent.

Figure A.1 Logic diagram to demonstrate event ...

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Verilog HDL Design Examples

by Joseph Cavanagh

Appendix A

Event Queue

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