Chapter 5. Loop 3
The final loop in this book will refine and extend your understanding of VHDL by introducing the concept and mechanisms of reuse. One key aspect to reuse is the awareness of the existing Institute of Electrical and Electronics Engineers (IEEE) libraries and the commonly used packages within them.
Finally, we will revise the UART test bench to both incorporate reuse concepts and to enhance your ability to write a solid VHDL test bench.
5.1. Introducing Concept of Reuse
Reuse is a much-touted term that has not seen the acceptance that it should. The concept of reuse is simple – build it in a generic fashion once, then use it many times, in many different modules and projects.
Two challenges that have hindered reuse are as follows: ...

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