VHDL 101

Appendix. A Quick Reference

A.1. Language Constructs

Concurrent Statements	Sequential Statements
Unconditional assignment	target <= expression; z <= x OR y; mVec <= qVec and X”0F”;	↔	signal_target <= expression; z <= x OR y; mVec <= qVec and X”0F”;
			variable_target: = expression; z: = x OR y; mVec: = qVec and X”0F”;
Conditional assignment	target <= expr when condition else expr when condition else expr; z <= x when (q = ‘1’) else y when (g = ‘0’) else ‘0’;	↔	if (cond) then <statements> elsif (cond) then <statements> else <statements> end if; if (q = ‘1’) then z <= x; elsif (g = ‘0’) then z <= y; else z <= ‘0’; end if;
Selective assignment	with selector select target <= expression when choice, expression when choice, …; with (button) select response <= ‘Y’ when ...