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Vhdl for Logic Synthesis, Third Edition by Andrew Rushton

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Chapter 5

Operators

The VHDL language has a set of standard operators that can be used to perform comparisons, form boolean equations and perform arithmetic. This set of operators is the toolkit that is used to build up RTL models.

This chapter introduces the built-in operators and what they do, with an explanation of the rules that VHDL uses to decide the order of precedence when calculating a complicated expression.

5.1 The Standard Operators

The full set of operators in VHDL is listed here:

not inversion
and and function
nand not-and function
or or function
nor not-or function
xor exclusive-or function (bitwise inequality)
xnor exclusive-nor function (bitwise equality)
= equality
/= inequality
>= greater-than or equal
> greater-than
<= less-than or equal
< less-than
sll shift-left logical
srl shift-right logical
sla shift-left arithmetic
sra shift-right arithmetic
rol rotate left
ror rotate right
+ addition
subtraction
+ plus sign
minus sign
multiplication
/ division
mod modulo arithmetic
rem remainder after division
∗∗ exponentiation
abs absolute value
& concatenation.

5.2 Operator Precedence

Operators are classified by the standard as logical, relational, adding, sign, multiplying and miscellaneous. The reason for classifying the operators is to allow for operator precedence. This is not the same classification I have used in the rest of the book, which is simpler and groups operators by what they do, rather ...

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