Vhdl for Logic Synthesis, Third Edition

Chapter 9

Registers

This chapter covers the VHDL required to describe registers. Throughout this chapter and the rest of the book, the term register will be used to refer to a flip-flop or a bank of flip-flops with common controls.

This chapter explains how a register is modelled, how this model is mapped onto flip-flops by a synthesiser. It then describes how to model other behaviour, such as resettable registers, gated registers. All of these models use synthesis templates to ensure the correct mapping from VHDL model to hardware.

9.1 Basic D-Type Register

The best way to explain how to describe a register in VHDL is with an example. The example is a complete VHDL design, with an entity and architecture. This is just to show the context; it is not a requirement that each register is described as a separate design unit and it is rare to do so.

The only recommended way to describe a register for logic synthesis is with a process. There are other ways of obtaining similar behaviour for simulation, but they will not necessarily be synthesisable.

library ieee;

use ieee.std_logic_1164.all;

entity Dtype is

  port (d, ck : in std_logic;

        q : out std_logic);

end;

architecture behaviour of Dtype is

begin

  process

  begin

    wait until rising_edge(ck);

    q <= d;

  end process;

end;

The register is described by the process statement. The process is recognised as a register because it matches a template built into the synthesiser. This is an example of a VHDL construct that ...