Vhdl for Logic Synthesis, Third Edition

Chapter 11

Subprograms

Subprograms in VHDL are very much like subprograms in software programming languages. They contain series of sequential statements and can be called from anywhere in a VHDL model to execute those statements.

There are two types of subprogram in VHDL: the function and the procedure. Operators (for example the add operator "+") are functions.

The use of subprograms in VHDL for logic synthesis is to carry out commonly repeated operations. Hierarchy is implemented using components (Chapter 10). This chapter describes how to write subprograms and when it is appropriate to do so.

11.1 The Role of Subprograms

In software languages, subprograms are the natural form of hierarchy. A task is broken down into subtasks, each of which is written as a subprogram and called from other subprograms.

However, in VHDL, the natural form of hierarchy is the entity/architecture pair, which is then invoked as a component. Designs should be partitioned into separate components, each of which can be simulated and tested in isolation. These components can then be used as instances (the term is instantiated) in a higher-level architecture.

It is easy for VHDL users with a software background to fall into the trap of using VHDL like a software language and partitioning a problem into subprograms. This is always a mistake. Bear in mind that only processes can model registers, and subprograms cannot contain processes because they contain only sequential statements, so subprograms must ...