This chapter is a mopping-up chapter to cover a few hardware structures that are important but that haven't fitted into the earlier chapters. These special structures have been collected together here.
The first special structure is the tristate driver, how to model this in simulation using a synthesis template and how to model tristate buses.
Then finite state machines (FSMs) are covered. These are often used to implement controllers. A variety of templates are described that provide Moore machines, Mealy machines and FSMs with either combinational or registered outputs.
The next section covers memories, which can be implemented as register banks or converted into RAMs using RAM inference. A number of different templates are described that allow different types of RAM to be inferred.
Finally, decoders are described, which can be converted into ROMs using ROM inference.
There are two aspects to the modelling of tristate systems in VHDL. One covers the modelling of tristate drivers. The other is the modelling of tristate buses.
Tristate drivers are hardware structures that have to be recognised as templates, since there is no direct mapping from VHDL to tristate drivers. In other words, a synthesiser has to perform tristate inference, just as it has to perform latch inference and register inference.
The most common tristate driver template uses sequential VHDL to model tristate behaviour. This means that tristate drivers must be modelled ...