Vhdl for Logic Synthesis, Third Edition

Chapter 14

Libraries

Libraries are an important concept in VHDL, and yet they seem to cause a lot of problems and confusion amongst VHDL users. For that reason, this short chapter has been included to give a brief overview of libraries and recommendations on how to organise your work in libraries.

14.1 The Library

A library can be regarded as a container that contains compiled design units. A library can also be regarded as the destination for VHDL compilers.

When a VHDL source file is compiled (or analysed seems to be the preferred term in VHDL circles) into a VHDL system, it is split into separate design units. If a source file contains, say, ten design units then the file will be split into ten parts. Each design unit is then analysed in isolation and the compiled result, an intermediate form, is saved into a library. At the end of the analysis, the library will contain ten design units.

Also, when a simulation is run, a design unit is simulated directly in its library, so the original source file is not involved in the simulation process. Instead, the model is built by assembling all of the intermediate forms for all of the design units in the model into a runnable model.

Typically, a simulator will analyse VHDL source into object code – so object code is the intermediate form. Then, the simulation consists of linking the object code into a program that is then run. However, this is not the only approach possible and some simulators use different techniques.

A simulator and ...