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Vhdl for Logic Synthesis, Third Edition

Name: Vhdl for Logic Synthesis, Third Edition
Author: Andrew Rushton
ISBN: 9780470688472

by Andrew Rushton

May 2011

Intermediate to advanced

484 pages

12h 50m

English

Wiley

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Cover
Title Page
Copyright
Preface
List of Figures
List of Tables
Chapter 1: Introduction
1.1 The VHDL Design Cycle1.2 The Origins of VHDL1.3 The Standardisation Process1.4 Unification of VHDL Standards1.5 Portability
Chapter 2: Register-Transfer Level Design
2.1 The RTL Design Stages2.2 Example Circuit2.3 Identify the Data Operations2.4 Determine the Data Precision2.5 Choose Resources to Provide2.6 Allocate Operations to Resources2.7 Design the Controller2.8 Design the Reset Mechanism2.9 VHDL Description of the RTL Design2.10 Synthesis Results
Chapter 3: Combinational Logic
3.1 Design Units3.2 Entities and Architectures3.3 Simulation Model3.4 Synthesis Templates3.5 Signals and Ports3.6 Initial Values3.7 Simple Signal Assignments3.8 Conditional Signal Assignments3.9 Selected Signal Assignment3.10 Worked Example
Chapter 4: Basic Types
4.1 Synthesisable Types4.2 Standard Types4.3 Standard Operators4.4 Type Bit4.5 Type Boolean4.6 Integer Types4.7 Enumeration Types4.8 Multi-Valued Logic Types4.9 Records4.10 Arrays4.11 Aggregates, Strings and Bit-Strings4.12 Attributes4.13 More on Selected Signal Assignments

Chapter 5: Operators
5.1 The Standard Operators5.2 Operator Precedence5.3 Boolean Operators5.4 Comparison Operators5.5 Shifting Operators5.6 Arithmetic Operators5.7 Concatenation Operator
Chapter 6: Synthesis Types
6.1 Synthesis Type System6.2 Making the Packages Visible6.3 Logic Types – Std_Logic_11646.4 Numeric Types – Numeric_Std6.5 Fixed-Point Types – Fixed_Pkg6.6 Floating-Point Types – Float_Pkg6.7 Type Conversions6.8 Constant Values6.9 Mixing Types in Expressions6.10 Top-Level Interface
Chapter 7: Std_Logic_Arith
7.1 The Std_Logic_Arith Package7.2 Contents of Std_Logic_Arith7.3 Type Conversions7.4 Constant Values7.5 Mixing Types in Expressions
Chapter 8: Sequential VHDL
8.1 Processes8.2 Signal Assignments8.3 Variables8.4 If Statements8.5 Case Statements8.6 Latch Inference8.7 Loops8.8 Worked Example
Chapter 9: Registers
9.1 Basic D-Type Register9.2 Simulation Model9.3 Synthesis Model9.4 Register Templates9.5 Register Types9.6 Clock Types9.7 Clock Gating9.8 Data Gating9.9 Asynchronous Reset9.10 Synchronous Reset9.11 Registered Variables9.12 Initial Values
Chapter 10: Hierarchy
10.1 The Role of Components10.2 Indirect Binding10.3 Direct Binding10.4 Component Packages10.5 Parameterised Components10.6 Generate Statements10.7 Worked Examples
Chapter 11: Subprograms
11.1 The Role of Subprograms11.2 Functions11.3 Operators11.4 Type Conversions11.5 Procedures11.6 Declaring Subprograms11.7 Worked Example
Chapter 12: Special Structures
12.1 Tristates12.2 Finite State Machines12.3 RAMs and Register Banks12.4 Decoders and ROMs
Chapter 13: Test Benches
13.1 Test Benches13.2 Combinational Test Bench13.3 Verifying Responses13.4 Clocks and Resets13.5 Other Standard Types13.6 Don't Care Outputs13.7 Printing Response Values13.8 Using TextIO to Read Data Files13.9 Reading Standard Types13.10 TextIO Error Handling13.11 TextIO for Synthesis Types13.12 TextIO for User-Defined Types13.13 Worked Example
Chapter 14: Libraries
14.1 The Library14.2 Library Names14.3 Library Work14.4 Standard Libraries14.5 Organising Your Files14.6 Incremental Compilation
Chapter 15: Case Study
15.1 Specification15.2 System-Level Design15.3 RTL Design15.4 Trial Synthesis15.5 Testing the Design15.6 Floating-Point Version15.7 Final Synthesis15.8 Generic Version15.9 Conclusions
Appendix A: Package Listings
A.1 Package StandardA.2 Package Standard_AdditionsA.3 Package Std_Logic_1164A.4 Package Std_Logic_1164_AdditionsA.5 Package Numeric_StdA.6 Package Numeric_Std_AdditionsA.7 Package Fixed_Float_TypesA.8 Package Fixed_PkgA.9 Package Float_PkgA.10 Package TextIOA.11 Package Standard_Textio_AdditionsA.12 Package Std_Logic_ArithA.13 Package Math_Real
Appendix B: Syntax Reference
B.1 KeywordsB.2 Design UnitsB.3 Concurrent StatementsB.4 Sequential StatementsB.5 ExpressionsB.6 Declarations
References
Index

Content preview from Vhdl for Logic Synthesis, Third Edition

Chapter 15

Case Study

This case study brings together all the principles established in the rest of the book. It covers the RTL design of a synchronous system, the design of test benches to test it and the results from those tests.

The example is a low-pass digital filter and the case study shows how the original specification is gradually converted into an RTL design suitable for logic synthesis, with an exploration of the design space to find an optimum data representation and precision for the filter calculations.

The example also shows how test benches are written for this design that explore the frequency response of the filter and verify that the specification has been met.

15.1 Specification

The specification is a Low-Pass digital filter with the following characteristics:

Maximum Frequency: 80 kHz;

Cut-off Frequency: 20 kHz;

Transition Bandwidth: 10 kHz;

Stop-band Attenuation: 18 dB.

The maximum frequency is the highest input frequency that the filter can handle.

The cut-off frequency is the end of the pass band and the frequency at which the gain should start to drop off.

The transition bandwidth is the frequency gap between the cut-off frequency at the end of the pass band and the beginning of the stop band.

The stop-band attenuation is the reduction in signal power for frequencies in the stop-band.

For this example the cut-off frequency is set at 20 kHz, the transition bandwidth is 10 kHz, so the stop band starts at 30 kHz at which point the specification requires ...

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Vhdl for Logic Synthesis, Third Edition

by Andrew Rushton

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.