Vhdl for Logic Synthesis, Third Edition

Preface

The motivation for writing this book originally came from my own frustration at the lack of a synthesis-orientated book when I was learning VHDL. Not only was there a lack of information on the synthesis subset, but I found that most books on VHDL had a common problem: they described absolutely everything in an indiscriminate way, and left the reader to sort out which bits were relevant and useful. It was extremely difficult to deduce the synthesis subset from this approach.

In this book, I cover the features of VHDL that you need to know for logic synthesis, from a hardware designer's viewpoint. Each feature of the language is explained in hardware terms and the mapping from VHDL to hardware is shown. Furthermore, only the synthesisable features are presented and so there is no possibility of confusion between synthesisable and non-synthesisable features.

The exception to this rule is the chapter on test benches. Even hardware designers using the language exclusively for logic synthesis will have to write test benches and since these are not synthesised, the whole language becomes available (but not necessarily useful). So the test bench chapter introduces those parts of the language that are relevant and useful for writing test benches.

The reason that a book like this is necessary is that VHDL is a very large and clumsy language. It suffers from design-by-committee and as a result is difficult to learn, has many useless features, and I can say from my own experience, ...