VHDL: Programming by Example

CHAPTER 16

Place and Route

This chapter discusses the process of implementing the synthesis netlist of the CPU design into a target FPGA device. The place and route tools read the netlist, extract the components and nets from the netlist, place the components on the target device, and interconnect the components using the specified interconnections. After the place and route process is complete, the designer has an implementation of the design in the target technology. The implementation still needs to be verified for logical and timing correctness.

Place and Route Process

The place and route process places each macro from the synthesis netlist ...