O'Reilly logo

VHDL by Gaganpreet Kaur

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

5

Dataflow Modelling

CHAPTER OBJECTIVES
  • Introduction to dataflow modelling
  • Understand the differences between concurrent and sequential signal assignment statements
  • Explore the concurrency of VHDL
  • Learn about conditional assignment statements
  • Use of blocks in VHDL
  • Use of generate statements to allow iterations and looping in concurrent modelling
  • Concurrent assertion statements
5.1 INTRODUCTION

Dataflow modelling describes the architecture of the entity under design without describing its components in terms of flow of data from input towards output. This style is nearest to RTL description of the circuit. Dataflow modelling is concurrent style of modelling in VHDL, that is, unlike behavioural modelling the order of statements is not important ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required