- Introduction to dataflow modelling
- Understand the differences between concurrent and sequential signal assignment statements
- Explore the concurrency of VHDL
- Learn about conditional assignment statements
- Use of blocks in VHDL
- Use of generate statements to allow iterations and looping in concurrent modelling
- Concurrent assertion statements
Dataflow modelling describes the architecture of the entity under design without describing its components in terms of flow of data from input towards output. This style is nearest to RTL description of the circuit. Dataflow modelling is concurrent style of modelling in VHDL, that is, unlike behavioural modelling the order of statements is not important ...