VHDL

6

Structural Modelling

CHAPTER OBJECTIVES

• Understand hierarchical modelling in VHDL
• Advantages of using components in design
• To define and instantiate a component
• Using generics

6.1 INTRODUCTION

Structural modelling is the simplest style of modelling and the lowest level of abstraction. It describes the circuit design in terms of its components. Structural style is nearest to gate-level simulation of the circuit. In this, the circuit is represented as a set of interconnected components. It facilitates hierarchical modelling of circuit’s particularly large complex designs. For complex designs, top-level entity is usually modelled in the structural form, whereas lower-level entities depending on the level of complexity, are modelled at ...