Every output signal created has associated with it driver(s) which holds its values.
In this signal s is driven by the expression value computed by ‘xor’ operation of ‘a’ and ‘b’. But at times, situation may arise where the same signal has more than one driving statements associated with it. This gives rise to following situations that are encountered in VHDL:
s<= 1 after 3 ns, 4 after 6 ns, 12 after 20 ns
s<= a; ...