VHDL

10

Testbenches

CHAPTER OBJECTIVES

• To know what is testbench
• Writing a testbench
• Verification of VHDL designs using testbenches
• Using test vectors in files for testbenches

10.1 INTRODUCTION

Verification of the circuit functionality is done as the first step once complete VHDL code for circuit has been coded. Verification of design without actual hardware in place is done using simulation. For simulating any design two things are required: design to be tested and stimulus to inputs. Two approaches are used in VHDL for simulation: one is assigning input values in simulation window and getting the output waveforms and the other is using testbenches.

Testbench is different from VHDL simulation of the circuit, which uses run-time assignment ...