book

VHDL

Name: VHDL
Author: Gaganpreet Kaur
ISBN: 9788131732113

by Gaganpreet Kaur

January 2011

Intermediate to advanced

340 pages

7h 30m

English

Pearson Education India

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Cover
Title Page
Contents
About the Author
Preface
Lesson Plan
Chapter 1. Digital Design Flow
1.1 Introduction1.1.1 Design Flow1.1.2 EDA Tools for Design1.2 Role of Hdl1.2.1 Introduction to HDLs1.2.2 Evolution of HDLs1.2.3 Different HDLsSummaryQuestions
Chapter 2. Introduction to VHDL
2.1 History of VHDL2.2 Comparison Between VHDL and Verilog2.3 Features of VHDL2.4 Basic Terminologies of VHDL2.5 Levels of Hardware Abstraction2.5.1 Overview2.5.2 Entity Declaration2.5.3 Architecture Body2.5.4 Styles of Modelling2.5.5 A Simple Coding Example in VHDL2.6 Delay Models in VHDL2.6.1 Inertial Delay Model2.6.2 Transport Delay Model2.6.3 Delta Delay Model2.6.4 Differences Between Inertial Delay and Transport DelaySummaryQuestions
Chapter 3. Basic Language Elements
3.1 Introduction3.1.1 Identifiers3.2 Data Objects3.2.1 Constant3.2.2 Variable3.2.3 Signals3.3 Data Types3.3.1 Predefined Types3.3.2 Scalar Type3.3.3 Composite Type3.3.4 Access Type3.3.5 File Type3.4 Operators3.4.1 Arithmetic Operators3.4.2 Logical Operators3.4.3 Relational Operators3.4.4 Shift-and-Rotate Operators3.4.5 Miscellaneous OperatorsSummaryQuestions
Chapter 4. Behavioural Modelling
4.1 Introduction4.2 Sequential Vs Concurrent Statements4.3 Process Statement4.3.1 Sensitivity List4.4 Variables4.4.1 Differences Between a Signal and a Variable4.5 Sequential Statements4.5.1 If Statement4.5.2 Case Statement4.5.3 Loop Statement4.5.4 Wait Statement4.5.5 Assert Statement4.5.6 Exit Statement4.5.7 Next Statement4.5.8 Null Statement4.6 Postponed Processes4.7 Passive ProcessesSummaryQuestions

Chapter 5. Dataflow Modelling
5.1 Introduction5.2 Conditional Assignment Statements5.2.1 When-Else5.2.2 With-When-Select5.3 Block Statement5.4 Concurrent Assert Statement5.5 Concept of Delay in Concurrent LogicSummaryQuestions
Chapter 6. Structural Modelling
6.1 Introduction6.2 Component Declaration6.3 Component Instantiation6.4 Generics6.4.1 Introduction6.4.2 Generic Map6.4.3 Generics with Behavioural ModellingSummaryQuestions
Chapter 7. Subprograms and Overloading
7.1 Introduction7.2 Functions7.3 Using Functions7.3.1 Function in the Main Code7.3.2 Function Inside Package7.3.3 Scope of Function7.4 Types of Function7.5 Procedures7.6 Using Procedures7.7 Differences Between Functions and Procedures7.8 Overloading7.8.1 Subprogram Overloading7.8.2 Overloading OperatorsSummaryQuestions
Chapter 8. Configurations and Packages
8.1 Introduction to Configurations8.1.1 Need for Configurations8.2 Writing Configuration8.2.1 Entity–Architecture Pair Configuration8.2.2 Component–Entity Binding Configuration Specification8.3 Introduction to Packages8.4 Writing a Package8.5 Using PackageSummaryQuestions
Chapter 9. Advanced Programming Concepts
9.1 Multiple Drivers9.2 Attributes9.2.1 Value Attributes9.2.2 Function Attributes9.2.3 Type Attributes9.2.4 Range Attributes9.3 Libraries9.4 Alias9.5 Signatures9.6 Qualified Expressions9.7 Generate Statement9.8 Null TransactionsSummaryQuestions
Chapter 10. Testbenches
10.1 Introduction10.1.1 Advantages of Using Testbenches10.2 Writing a Testbench10.3 Waveform GenerationSummaryQuestions
Chapter 11. Circuit Synthesis
11.1 Introduction11.2 Differences Between Simulation and Synthesis11.3 Synthesis Flow11.4 Synthesizing Data Types11.5 Synthesis of Combinational Logic11.6 Synthesizing Sequential Logic11.7 Modelling Finite State MachinesSummaryQuestions
Chapter 12. Embedded Design Using VHDL
12.1 Introduction12.2 Architecture of Embedded System12.3 Design Flow for Embedded System Design12.4 Issues in Embedded System Design12.4.1 Design Optimizations12.5 Limitations of VHDL in the Embedded System DesignSummaryQuestions
Chapter 13. Microcomputer Design
13.1 Introduction13.1.1 Basic Components of a Microcomputer13.2 Implementation of Microcomputer using VHDLSummaryQuestions
Chapter 14. Programmable Logic Devices
14.1 Introduction14.2 Types of Plds14.2.1 Plas (Programmable Logic Arrays)14.2.2 Pals14.2.3 Registered PALs14.2.4 Gals (Generic Array Logic)14.2.5 Macrocell Structure14.3 Advantages of Using Plds14.4 Cplds And Fpgas14.4.1 CPLDs14.4.2 Fpgas (Field Programmable Gate Array)14.4.3 Differences Between Fpgas and Cplds14.4.4 Implementation Using Fpgas and CpldsSummaryQuestions
Chapter 15. Case Study—Genetic Algorithm Processor
15.1 Introduction to Genetic Algorithms15.2 Hardware Ga15.3 Architecture of Gap15.4 Implementing the Modules for Gap15.4.1 Processing Unit15.5 Future Scope
Additional Case Studies
Appendix A. Xilinx 9.1 Tutorial
Appendix B. Synthesizable Constructs of VHDL-93 and VHDL-2008
Appendix C. VHDL-2008: New Features
Appendix D. VHDL-AMS
Appendix E. Unsolved Design Problems
Acknowledgements
Copyright

Content preview from VHDL

10 Testbenches

CHAPTER OBJECTIVES

To know what is testbench
Writing a testbench
Verification of VHDL designs using testbenches
Using test vectors in files for testbenches

10.1 INTRODUCTION

Verification of the circuit functionality is done as the first step once complete VHDL code for circuit has been coded. Verification of design without actual hardware in place is done using simulation. For simulating any design two things are required: design to be tested and stimulus to inputs. Two approaches are used in VHDL for simulation: one is assigning input values in simulation window and getting the output waveforms and the other is using testbenches.

Testbench is different from VHDL simulation of the circuit, which uses run-time assignment ...

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