VLSI Design Methodology Development, First Edition

Chapter 10. Layout Parasitic Extraction and Electrical Modeling

10.1 Introduction

All electrical analysis flows are based on a methodology that incorporates a transistor or cell-based netlist with corresponding electrical parasitics from the layout interconnects annotated to the netlist to create a complete electrical model. There are layout parasitic extraction (LPE) algorithm trade-offs in terms of electrical accuracy, the number of RLC parasitic elements generated, RLC element reduction strategies (while maintaining a model of sufficient accuracy), and the EDA tool compute resources and runtime.

Traditionally, LPE tools from EDA vendors have used either of two methods for capacitance calculation, with distinct characteristics relative to ...