Skip to Main Content
VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 12. Noise Analysis

12.1 Introduction to Noise Analysis

With the increasing percentage of coupling capacitance to total load capacitance on nets in submicron VLSI process nodes, it is necessary to assess the potential impact of coupled transients on each interconnect to ensure that robust circuit behavior is maintained. Noise analysis is addressed in three different methodology flows:

  • Noise impact on delay, integrated with static timing analysis—A capacitive coupling event to a net in transition alters the delay and slew at the net fan-outs.

  • Static noise analysis (a sign-off flow)—A capacitive coupling event to a quiescent net results in current injected on the net; this current flows back to the active driver and to the net fan-outs. ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Modern VLSI Design: System-on-Chip Design, Third Edition

Modern VLSI Design: System-on-Chip Design, Third Edition

Wayne Wolf
Digital Logic Design, 4th Edition

Digital Logic Design, 4th Edition

Brian Holdsworth, Clive Woods

Publisher Resources

ISBN: 9780135657645