VLSI Design Methodology Development, First Edition

Chapter 12. Noise Analysis

12.1 Introduction to Noise Analysis

With the increasing percentage of coupling capacitance to total load capacitance on nets in submicron VLSI process nodes, it is necessary to assess the potential impact of coupled transients on each interconnect to ensure that robust circuit behavior is maintained. Noise analysis is addressed in three different methodology flows:

• Noise impact on delay, integrated with static timing analysis—A capacitive coupling event to a net in transition alters the delay and slew at the net fan-outs.

• Static noise analysis (a sign-off flow)—A capacitive coupling event to a quiescent net results in current injected on the net; this current flows back to the active driver and to the net fan-outs. ...