REFERENCES

1. A. Avizienis, “Signed digit number representation for fast parallel arithmetic,” IRE Trans. on Electronic Computers, vol. EC-10, pp. 389–400, Sept. 1961.

2. S. C. Knowles, J. G. McWhirter, R. F. Woods, and J. V. McCanny, “Bit-level systolic architectures for high performance IIR filtering,” Journal of VLSI Signal Processing, pp. 297–312, 1989.

3. D. S. Phatak and I. Koren, “Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains,” IEEE Trans. on Computers, vol. 43, no. 8, pp. 880–891, Aug. 1994.

4. A. Guyot, Y. Herreros, and J. Muller, “JANUS, an on-line multiplier/divider for manipulating large numbers,” in Proc. of 9th Symposium on Computer Arithmetic, pp. 106–111, 1989.

5. N. Takagi, H. Yassura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. on Computers, vol. C-34, no. 9, pp. 789–796, Sept. 1985.

6. J. Duprat, Y. Herreros, and J. Muller, “Some results about on-line computation of functions,” in Proc. of 9th Symposium on Computer Arithmetic, pp. 112–118, 1989.

7. A. Skaf and A. Guyot, “VLSI design of on-line add/multiply algorithms,” in Proc. of ICCD’93, (Cambridge, Massachusetts), pp. 264–267, Oct. 1993.

8. K. S. Trivedi and M. D. Ercegovac, “On-line algorithms for division and multiplication,” IEEE Trans. on Computers, vol. C-26, no. 7, pp. 681–687, July 1977.

9. M. J. Irwin and R. M. Owens, “Design issues in digit serial ...

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