Chapter 3. Logic and Fault Simulation
Jiun-Lang HuangNational Taiwan University, Taipei, Taiwan
James C.-M. LiNational Taiwan University, Taipei, Taiwan
Duncan M. (Hank) WalkerTexas A&M University, College Station, Texas
About this Chapter
Simulation is a powerful set of techniques that are used heavily in digital circuit verification, test development, design debug, and diagnosis. During the design stage, logic simulation is performed to help verify whether the design meets its specifications and contains any design errors. It also helps locate these design errors that escape to fabrication during design debug. In test development, faulty circuit behavior is simulated with a set of test patterns to assess the pattern quality and guide further pattern ...