Wireless Transceiver Architecture

8 Transceiver Architectures

The underlying assumption for line-up budgeting, as illustrated in Chapter 7, is that there is enough flexibility in the parameters of the various blocks in the line-up to ensure that the overall requirements can be fulfilled. However, in real life implementations, the tuning range of the parameters is necessarily limited. This may lead to one stage in the line-up behaving as a bottleneck. Changing the architecture of the line-up is one solution to this kind of problem.

We therefore review some classical architectures in order to understand the associated limitations. Obviously, our aim is not to be exhaustive as we can basically imagine as many transceiver architectures as we want. Rather, it is to illustrate through a review of representative structures how to conceive a transceiver at a system level. This means trying to understand how to manage some of the limitations of a given architecture through its modification. In this chapter, the modifications we are referring to have to be understood at the RF/analog implementation level. The same can be said of algorithms, as will be discussed in Chapter 9 through some practical examples.

8.1 Transmitters

Let us start by discussing the transmit side. Basically, from the signal processing point of view, there are two families of architectures, depending on the decomposition of the complex modulating waveform we want to upconvert. More precisely, given the possibility of decomposing this complex signal ...