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Computer Systems, 4th Edition

Name: Computer Systems, 4th Edition
Author: J. Stanley Warford
ISBN: 9780763783075

by J. Stanley Warford

February 2009

Intermediate to advanced

700 pages

20h 6m

English

Jones & Bartlett Learning

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Cover
Title Page
Copyright
Dedication
Preface
Contents
Level 7 Application
Chapter 1 Computer Systems
1.1 Levels of AbstractionAbstraction in ArtAbstraction in DocumentsAbstraction in OrganizationsAbstraction in MachinesAbstraction in Computer Systems1.2 HardwareInput DevicesOutput DevicesMain MemoryCentral Processing Unit1.3 SoftwareOperating SystemsSoftware Analysis and Design1.4 Database SystemsRelationsQueriesStructure of the LanguageSummaryExercises
Level 6 High-Order Language
Chapter 2 C++
2.1 VariablesThe C++ CompilerMachine IndependenceThe C++ Memory ModelGlobal Variables and Assignment StatementsLocal Variables2.2 Flow of ControlThe If/Else StatementThe Switch StatementThe While LoopThe Do LoopArrays and the For Loop2.3 FunctionsVoid Functions and Call-By-Value ParametersFunctionsCall-By-Reference Parameters2.4 RecursionA Factorial FunctionThinking RecursivelyRecursive AdditionA Binomial Coefficient FunctionReversing the Elements of an ArrayTowers of HanoiMutual RecursionThe Cost of Recursion2.5 Dynamic Memory AllocationPointersStructuresLinked Data StructuresSummaryExercises

Level 3 Instruction Set Architecture
Chapter 3 Information Representation
3.1 Unsigned Binary RepresentationBinary StorageIntegersBase ConversionsRange for Unsigned IntegersUnsigned AdditionThe Carry Bit3.2 Two’s Complement Binary RepresentationTwo’s Complement RangeBase ConversionsThe Number LineThe Overflow BitThe Negative and Zero Bits3.3 Operations in BinaryLogical OperatorsRegister Transfer LanguageArithmetic OperatorsRotate Operators3.4 Hexadecimal and Character RepresentationsHexadecimalBase ConversionsCharacters3.5 Floating Point RepresentationBinary FractionsExcess RepresentationsThe Hidden BitSpecial ValuesThe IEEE 754 Floating Point Standard3.6 Representations Across LevelsAlternative RepresentationsModelsSummaryExercises
Chapter 4 Computer Architecture
4.1 HardwareCentral Processing Unit (CPU)Main MemoryInput DeviceOutput DeviceData and ControlInstruction Format4.2 Direct AddressingThe Stop InstructionThe Load InstructionThe Store InstructionThe Add InstructionThe Subtract InstructionThe And and Or InstructionsThe Invert and Negate InstructionsThe Load Byte and Store Byte InstructionsThe Character Input and Ouput Instructions4.3 von Neumann MachinesThe von Neumann Execution CycleA Character Output Programvon Neumann BugsA Character Input ProgramConverting Decimal to ASCIIA Self-Modifying Program4.4 Programming at Level ISA3Read-Only MemoryThe Pep/8 Operating SystemUsing the Pep/8 SystemSummaryExercises
Level 5 Assembly
Chapter 5 Assembly Language
5.1 AssemblersInstruction MnemonicsPseudo-OperationsThe .ASCII and .END Pseudo-opsAssemblersThe .BLOCK Pseudo-opThe .WORD and .BYTE Pseudo-opsUsing the Pep/8 AssemblerCross Assemblers5.2 Immediate Addressing and the Trap InstructionsImmediate AddressingThe DECI, DECO, and BR InstructionsThe STRO InstructionInterpreting Bit PatternsDisassemblers5.3 SymbolsA Program with SymbolsA von Neumann Illustration5.4 Translating from Level HOL6The cout StatementVariables and TypesGlobal Variables and Assignment StatementsType CompatibilityPep/8 Symbol TracerThe Shift and Rotate InstructionsConstants and .EQUATEPlacement of Instructions and DataSummaryExercises
Chapter 6 Compiling to the Assembly Level
6.1 Stack Addressing and Local VariablesStack-Relative AddressingAccessing the Run-Time StackLocal Variables6.2 Branching Instructions and Flow of ControlTranslating the If StatementOptimizing CompilersTranslating the If/Else StatementTranslating the While LoopTranslating the Do LoopTranslating the For LoopSpaghetti CodeFlow of Control in Early LanguagesThe Structured Programming TheoremThe Goto Controversy6.3 Function Calls and ParametersTranslating a Function CallTranslating Call-By-Value Parameters with Global VariablesTranslating Call-By-Value Parameters with Local VariablesTranslating Non-Void Function CallsTranslating Call-By-Reference Parameters with Global VariablesTranslating Call-By-Reference Parameters with Local VariablesTranslating Boolean Types6.4 Indexed Addressing and ArraysTranslating Global ArraysTranslating Local ArraysTranslating Arrays Passed as ParametersTranslating the Switch Statement6.5 Dynamic Memory AllocationTranslating Global PointersTranslating Local PointersTranslating StructuresTranslating Linked Data StructuresSummaryExercises
Chapter 7 Language Translation Principles
7.1 Languages, Grammars, and ParsingConcatenationLanguagesGrammarsA Grammar for C++ IdentifiersA Grammar for Signed IntegersA Context-Sensitive GrammarThe Parsing ProblemA Grammar for ExpressionsA C++ Subset GrammarContext Sensitivity of C++7.2 Finite State MachinesAn FSM to Parse an IdentifierSimplified Finite State MachinesNondeterministic Finite State MachinesMachines with Empty TransitionsMultiple Token Recognizers7.3 Implementing Finite State MachinesA Table-Lookup ParserA Direct-Code ParserAn Input Buffer ClassA Multiple-Token Parser7.4 Code GenerationA Language TranslatorParser CharacteristicsSummaryExercises
Level 4 Operating System
Chapter 8 Process Management
8.1 LoadersThe Pep/8 Operating SystemThe Pep/8 LoaderProgram Termination8.2 TrapsThe Trap MechanismThe RETTR InstructionThe Trap HandlersTrap Addressing Mode AssertionTrap Operand Address ComputationThe No-Operation Trap HandlersThe DECI Trap HandlerThe DECO Trap HandlerThe STRO Trap Handler and OS Vectors8.3 Concurrent ProcessesAsynchronous InterruptsProcesses in the Operating SystemMultiprocessingA Concurrent Processing ProgramCritical SectionsA First Attempt at Mutual ExclusionA Second Attempt at Mutual ExclusionsPeterson’s Algorithm for Mutual ExclusionSemaphoresCritical Sections with Semaphores8.4 DeadlocksResource Allocation GraphsDeadlock PolicySummaryExercises
Chapter 9 Storage Management
9.1 Memory AllocationUniprogrammingFixed-Partition MultiprogrammingLogical AddressesVariable-Partition MultiprogrammingPaging9.2 Virtual MemoryLarge Program BehaviorVirtual MemoryDemand PagingPage ReplacementPage-Replacement Algorithms9.3 File ManagementDisk DrivesFile AbstractionAllocation Techniques9.4 Error Detecting and Correcting CodesError-Detecting CodesCode RequirementsSingle-Error-Correcting Codes9.5 RAID Storage SystemsRAID Level 0: Nonredundant StripedRAID Level 1: MirroredRAID Levels 01 and 10: Striped and MirroredRAID Level 2: Memory-Style ECCRAID Level 3: Bit-Interleaved ParityRAID Level 4: Block-Interleaved ParityRAID Level 5: Block-Interleaved Distributed ParitySummaryExercises
Level 1 Logic Gate
Chapter 10 Combinational Circuits
10.1 Boolean Algebra and Logic GatesCombinational CircuitsTruth TablesBoolean AlgebraBoolean Algebra TheoremsProving ComplementsLogic DiagramsAlternate Representations10.2 Combinational AnalysisBoolean Expressions and Logic DiagramsTruth Tables and Boolean ExpressionsTwo-Level CircuitsThe Ubiquitous NAND10.3 Combinational DesignCanonical ExpressionsThree-Variable Karnaugh MapsFour-Variable Karnaugh MapsDual Karnaugh MapsDon’t-Care Conditions10.4 Combinational DevicesViewpointsMultiplexerBinary DecoderDemultiplexerAdderAdder/SubtracterArithmetic Logic UnitAbstraction at Level LG1SummaryExercises
Chapter 11 Sequential Circuits
11.1 Latches and Clocked Flip-FlopsThe SR LatchThe Clocked SR Flip-FlopThe Master–Slave SR Flip-FlopThe Basic Flip-FlopsThe JK Flip-FlopThe D Flip-FlopThe T Flip-FlopExcitation Tables11.2 Sequential Analysis and DesignA Sequential Analysis ProblemPreset and ClearSequential DesignA Sequential Design Problem11.3 Computer SubsystemsRegistersBusesMemory SubsystemsAddress DecodingA Two-Port Register BankSummaryExercises
Level 2 Microcode
Chapter 12 Computer Organization
12.1 Constructing a Level-ISA3 MachineThe Central Processing UnitImplementing the Store Byte InstructionImplementing the Add InstructionImplementing the Load InstructionImplementing the Arithmetic Shift Right Instruction12.2 Performance IssuesThe Bus WidthSpecialized Hardware UnitsThree Areas of OptimizationMicrocode12.3 The MIPS MachineLoad/Store ArchitecturesThe Instruction SetCache MemoriesMIPS Computer OrganizationPipelining12.4 ConclusionSimplifications in the ModelThe Big PictureSummaryExercises
Appendix Pep/8 Architecture
Solutions to Selected Exercises
Index

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