This final chapter shows the connection between the combinational and sequential circuits at Level LG1 and the machine at Level ISA3. It describes how hardware devices can be connected to form black boxes at successively higher levels of abstraction to eventually construct the Pep/8 computer.
12.1 Constructing a Level-ISA3 Machine
Figure 12.1 is a block diagram of the Pep/8 computer. It shows the CPU divided into a data section and a control section. The data section receives data from and sends data to the main memory subsystem. The control section issues the control signals to the data section and to the other components of the computer.
The Central Processing ...