book

32/64-Bit 80x86 Assembly Language Architecture

Name: 32/64-Bit 80x86 Assembly Language Architecture
Author: James Leiterman
ISBN: 9781449612702

by James Leiterman

August 2005

Intermediate to advanced

545 pages

9h 35m

English

Jones & Bartlett Learning

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Copyright
Preface
1. Introduction
Conventions Used in This BookCompanion CodeImage PatterningProcessor LegendNotes, Tips, and HintsPseudo VecPseudo Vec (x86) (3DNow!) (3DNow!+) (MMX) (MMX+) (SSE) (SSE2) (SSE3)Graphics 101 (x86) (3DNow!) (MMX)Algebraic LawI-VU-Q
2. Coding Standards
ConstantsData AlignmentStacks and Vectors3D Vector (Floating-Point)3D Quad Vector (Floating-Point)Compiler DataAssertionsMemory SystemsRamTest Memory Alignment TestMemory HeaderAllocate Memory (Malloc Wrapper)Release Memory (Free Wrapper)Allocate MemoryAllocate (Cleared) MemoryFree Memory — Pointer Is Set to NULLExercises
3. Processor Differential Insight
Processor OverviewHistoryThe 64-Bit Processor80x86 RegistersGeneral-Purpose RegistersREXSegment/Selector RegistersMMX RegistersXMM RegistersCPU Status Registers (EFLAGS/64-Bit RFLAGS)LAHF — Load AH FlagsSAHF — Save AH FlagsPUSHF/PUSHFD — Push EFLAGS onto StackPUSHFQ — Push RFLAGS onto StackPOPF/POPFD — Pop EFLAGS from StackPOPFQ — Pop RFLAGS from StackCLC — Clear (Reset) Carry FlagSTC — Set Carry FlagCMC — Complement Carry FlagNOP — No OperationFloating-Point 101Processor Data Type EncodingEMMS — Enter/Leave MMX StateFEMMS — Enter/Leave MMX StateDestination/Source OrientationsBig/Little-EndianAlignment Quickie(Un)aligned Memory AccessMOV/MOVQ — Move DataMove (Unaligned)Move (Aligned)Misaligned SSE(2) (128-bit)Aligned SSE(2) (128-bit)XCHG — Exchange (Swap) DataSystem Level FunctionalityIndirect Memory Addressinguint32 OddTable[ ]LEA — Load Effective AddressTranslation TableXLAT/XLATB — Translation Table LookupString InstructionsLODSB/LODSW/LODSD/LODSQ — Load StringREP LODSxSTOSB/STOSW/STOSD/STOSQ — Save StringREP/REPE/REPZ/REPNE/REPNZ — Repeat StringREP STOSxMOVSB/MOVSW/MOVSD/MOVSQ — Move StringREP MOVSxCLD/STD — Clear/Set Direction FlagSpecial (Non-Temporal) Memory InstructionsMOVNTx — Copy Using Non-Temporal HintMOVNTPS — Copy 4 × SPFP Using Non-Temporal HintMOVNTPD — Copy 2×DPFP Using Non-Temporal HintMASKMOVQ/MASKMOVDQU — Copy Selected BytesExercises
4. Bit Mangling
Boolean Logical ANDPseudo VecLogical Packed AND D=(AB)vmp_pand (x86) 32-bitvmp_pand (x86) 64-bitvmp_pand (MMX)vmp_pand (SSE2) Aligned Memoryvmp_pand (SSE2) Unaligned MemoryBoolean Logical ORPseudo VecLogical Packed OR D=(AB)Boolean Logical XOR (Exclusive OR)Pseudo VecLogical Packed XOR D=(AB)NOT — One's Complement NegationNEG — Two's Complement NegationToolBox Snippet — The Butterfly SwitchI-VU-QBoolean Logical ANDCPseudo VecLogical Packed ANDC D=(AB′)Exercises
5. Bit Wrangling
Logical Left ShiftingSHL/SAL - Shift (Logical/Arithmetic) LeftSHLD — Shift (Logical) Left (Double)PSLLx — Parallel Shift Left (Logical)Pseudo VecPacked Shift Left Logical 16×8-bit by n:{0...7}Pseudo Vec (x86)vmp_psllB (MMX) 16×8-bit VectorLogical Right ShiftingSHR — Shift (Logical) RightSHRD — Shift (Logical) Right (Double)PSRLx — Parallel Shift Right (Logical)Pseudo VecPacked Shift Right Logical 16×8-bit by n:{0...7}Arithmetic Right ShiftingSAR — Shift (Arithmetic) RightPSRAx — Packed Shift Right (Arithmetic)Pseudo VecRotate Left (or n-Right)ROL — Rotate LeftRCL — Rotate Carry LeftRotate RightROR — Rotate RightRCR — Rotate Carry RightBit ScanningBSF — Bit Scan ForwardBSR — Bit Scan ReverseToolBox Snippet — Get Bit CountGraphics 101 — Palette BitsExercises
6. Data Conversion
Data Interlacing, Exchanging, Unpacking, and MergingByte SwappingLittle-Endian(Big/Little)-Endian to (Big/Little)-Endian Data Relationship MacrosBSWAP — Byte SwapPSWAPD — Packed Swap Double WordData InterlacingPUNPCKLBW — Parallel Extend Lower from BytePUNPCKHBW — Parallel Extend Upper from BytePUNPCKLWD — Parallel Extend Lower from 16-BitPUNPCKHWD — Parallel Extend Upper from 16-BitPUNPCKLDQ — Parallel Extend Lower from 32-BitAlso: (Unpack and Interleave Low Packed SPFP)PUNPCKHDQ — Parallel Extend Upper from 32-BitALSO: (Unpack and Interleave High Packed SPFP)MOVSS — Move Scalar (SPFP)MOVQ2DQ — Move Scalar (1×32-Bit) MMX to XMMMOVDQ2Q — Move Scalar (1×32-bit) XMM to MMXMOVLPS — Move Low Packed (2×SPFP)MOVHPS — Move High Packed (2×SPFP)MOVLHPS — Move Low to High Packed (2×SPFP)MOVHLPS — Move High to Low Packed (2×SPFP)MOVSD — Move Scalar (1×DPFP)MOVLPD — Move Low Packed (1×DPFP)MOVHPD — Move High Packed (1×DPFP)PUNPCKLQDQ — Parallel Copy Lower (2×64-Bit)Also: (Unpack and Interleave Low Packed Double-Precision Floating-Point Values)PUNPCKHQDQ — Parallel Copy Upper (2×64-Bit)Also: (Unpack and Interleave High Packed Double-Precision Floating-Point Values)Swizzle, Shuffle, and SplatPINSRW — Shuffle (1×16-Bit) to (4×16-Bit)PSHUFW — Shuffle Packed Words (4×16-Bit)PSHUFLW — Shuffle Packed Low Words (4×16-Bit)PSHUFHW — Shuffle Packed High Words (4×16-Bit)PSHUFD — Shuffle Packed Double Words (4×32-Bit)SHUFPS — Shuffle Packed SPFP Values (4×SPFP)MOVSLDUP — Splat Packed Even SPFP to (4×SPFP)MOVSHDUP — Splat Packed Odd SPFP to (4×SPFP)MOVDDUP — Splat Lower DPFP to Packed (2×DPFP)SHUFPD — Shuffle Packed DPFP (2×64-Bit)Data Bit ExpansionCBW Convert Signed AL (Byte) to AX (Word)CWDE Convert Signed AX (Word) to EAX (DWord)CDQE Convert Signed EAX (DWord) to RAX (QWord)MOVSX/MOVSXD — Move with Sign ExtensionMOVZX — Move with Zero ExtensionCWD — Convert Signed AX (Word) to DX:AXCDQ — Convert Signed EAX (DWord) to EDX:EAXCQO — Convert Signed RAX (QWord) to RDX:RAXPEXTRW — Extract (4×16-bit) into Integer to (1×16)Data Bit Reduction (with Saturation)PACKSSWB — Packed Signed int16 to int8 with SaturationPACKUSWB — Packed uint16 to uint8 with SaturationPACKSSDW — Packed int32 to int16 with SaturationData Conversion (Integer : Float, Float : Integer, Float : Float)PI2FW — Convert Packed Even int16 to SPFPCVTDQ2PS — Convert Packed int32 to SPFPCVTPS2DQ — Convert Packed SPFP to int32CVTPI2PS — Convert Lo Packed int32 to SPFPCVTPS2PI — Convert Lo Packed SPFP to int32CVTSI2SS — Convert Scalar int32 to SPFPCVTDQ2PD — Convert Even Packed int32 to DPFPCVTPD2DQ — Convert Packed DPFP to Even int32CVTPD2PS — Convert Packed DPFP to Lo SPFPCVTPS2PD — Convert Lo Packed SPFP to DPFPCVTPD2PI — Convert Packed DPFP to int32CVTPI2PD — Convert Packed int32 to DPFPCVTSS2SI — Convert Scalar SPFP to int32/64CVTSD2SI — Convert Scalar DPFP to IntCVTSI2SD — Convert Scalar Int to DPFPCVTSD2SS — Convert Scalar DPFP to SPFPCVTSS2SD — Convert Scalar SPFP to DPFPExercises
7. Interger Math
General Integer MathADD — AddADC — Add with CarryINC — Increment by 1Thread-Safe IncrementXADD — Exchange and AddSUB — SubtractSBB — Subtract with BorrowDEC — Decrement by 1Thread-Safe DecrementPacked Addition and SubtractionPADDB/PADDW/PADDD/PADDQ Integer AdditionVector_{8/16/32/64}-Bit_Int_Addition_with_SaturationPSUBB/PSUBW/PSUBD/PSUBQ Integer SubtractionVector {8/16/32/64}-Bit Integer Subtraction with SaturationVector Addition and Subtraction (Fixed Point)Pseudo VecPseudo Vec (x86)vmp_paddB (MMX) 16×8-Bitvmp_paddB (SSE2) 16×8-BitAveragesPAVGB/PAVGUSB — N×8-Bit [Un]signed Integer AveragePAVGW — N×16-Bit [Un]signed Integer AverageSum of Absolute DifferencesPSADBW — N×8-Bit Sum of Absolute DifferencesInteger MultiplicationMUL — Unsigned Muliplication (Scalar)IMUL — Signed Multiplication (Scalar)Packed Integer MultiplicationPMULLW — N×16-Bit Parallel Multiplication (Lower)PMULHW/PMULHUW — N×16-Bit Parallel Multiplication (Upper)PMULHRW — Signed 4×16-Bit Multiplication with Rounding (Upper)Pseudo Vec (x86)(MMX Mul Low) 4×16-Bit(SSE2 Mul Low) 8×16-BitPMULUDQ — Unsigned N×32-Bit Multiply EvenPMADDWD — Signed N×16-Bit Parallel Multiplication — ADDInteger DivisionDIV — Unsigned DivisionIDIV — Signed DivisionExercises
8. Floating-Point Anyone?
The Floating-Point NumberFPU RegistersLoading/Storing Numbers and the FPU StackFLD — Floating-Point LoadFST/FSTP — FPU Floating-Point SaveFILD — FPU Integer LoadFIST/FISTP/FISTTP — FPU Integer SaveFPU ConstantsFXCHFINCSTP — FPU Increment Stack PointerFDECSTP — FPU Decrement Stack PointerFWAIT/WAITEMMS/FEMMSFNOPGeneral Math InstructionsFCHS — FPU Two's Complement ST(0) = – ST(0)FABS — FPU Absolute Value ST(0) = |ST(0)|FADD/FADDP/FIADD — FPU Addition D = ST(0) + AFSUB/FSUBP/FISUB — FPU Subtraction D = ST(0) – AFSUBR/FSUBRP/FISUBR — FPU Reverse Subtraction D = A – ST(0)FMUL/FMULP/FIMUL — FPU Multiplication D = ST(0) × AFDIV/FDIVP/FIDIV — FPU Division D = Dst ÷ SrcFDIVR/FDIVRP/FIDIVR — FPU Reverse Division D = Src ÷ DstFPREM — FPU Partial RemainderFPREM1 — FPU Partial RemainderFRNDINT — FPU Round to IntegerAdvanced Math InstructionsFSQRT — FPU ST(0) Square RootFSCALE — FPU Scale ST(0) = ST(0) << ST(1)F2XM1 — FPU ST(0) = 2ST(0) – 1FYL2X — FPU ST(0) = y log2xFYL2XP1 — FPU ST(0) = y log2(x+1)FXTRACT — FPU Extract Exponent and SignificandFloating-Point ComparisonFTST — FPU Test If ZeroFCOM/FCOMP/FCOMPP — FPU Unordered CMP FPFUCOM/FUCOMP/FUCOMPP — FPU Unordered CMP FPFCOMI/FCOMIP/FUCOMI/FUCOMIP — FPU A ? B and EFLAGSFICOM/FICOMP — FPU A ? BFCMOVcc — FPU Conditional MoveFXAM — FPU ExamineFPU BCD (Binary-Coded Decimal)FBLD — FPU (BCD Load)FBSTP — FPU (BCD Save and Pop ST(0))FPU TrigonometryFPTAN — FPU Partial TangentFPATAN — FPU Partial ArctangentFSINCOS — Sine and CosinePseudo VecPseudo Vec (x86)AMD-SDK3DSMax-SDKFSIN — FPU SineFCOS — FPU CosineFSINCOS — FPU Sine and Cosinevmp_SinCos (3DNow!)FPU System InstructionsFINIT/FNINIT — FPU InitFCLEX/FNCLEX — FPU Clear ExceptionsFFREE — FPU Free FP RegisterFSAVE/FNSAVE — FPU Save X87 FPU, MMX, SSE, SSE2FRSTOR — FPU Restore x87 StateFXSAVE — FPU Save x87 FPU, MMX, SSE, SSE2, SSE3FXRSTOR — FPU Restore x87 FPU, MMX, SSE, SSE2, SSE3FSTENV/FNSTENV — FPU Store x87 EnvironmentFLDENV — FPU Load x87 EnvironmentFSTCW/FNSTCW — FPU Store x87 Control WordFLDCW — FPU Load x87 Control WordFSTSW/FNSTSW — FPU Store x87 Status WordValidating (Invalid) Floating-PointExercises

9. Comparison
TEST — Logical Compare A BIndexed Bit TestingBT — Bit TestBTC — Bit Test and ComplementBTR — Bit Test and Reset (Clear)BTS — Bit Test and SetSETcc — Set Byte on ConditionComparing Operands and Setting EFLAGSCMP — Compare Two OperandsCOMISS — Compare Scalar SPFP, Set EFLAGSCOMISD — Compare Scalar DPFP, Set EFLAGSUCOMISS — Unordered Cmp Scalar SPFP, Set EFLAGSUCOMISD — Unordered Cmp Scalar DPFP, Set EFLAGSCMPSB/CMPSW/CMPSD/CMPSQ — Compare String OperandsCMP — Packed ComparisonCMPPS/CMPSS/CMPPD/CMPSD —Floating-PointPacked Compare if Equal to (=)Packed Compare if Greater Than or Equal (≥)Packed Compare if Greater Than (>)Extract Packed Sign MasksPMOVMSKB — Extract Packed Byte (Sign) MaskMOVMSKPS — Extract Packed SPFP Sign MaskMOVMSKPD — Extract Packed DPFP Sign MaskSCAS/SCASB/SCASW/SCASD/SCASQ —Scan StringREP SCASxCMOVcc — Conditional MoveCMPXCHG — Compare and ExchangeCMPXCHG8B — Compare and Exchange 64 BitsCMPXCHG16B — Compare and Exchange 128 BitsBoolean Operations upon Floating-Point NumbersANDPS — Logical AND of Packed SPFP D = A BANDPD — Logical AND of Packed DPFPPseudo Vec — (XMM) FABS — FP Absolute A = | A |Pseudo Vec — (3DNow!) FABS — FP Absolute A = | A |ORPS — Logical OR of Packed SPFP D = A BORPD — Logical OR of Packed DPFPXORPS — Logical XOR of Packed SPFP D = A BXORPD — Logical XOR of Packed DPFPPseudo Vec — FCHS — FP Change Sign A = – APseudo Vec (XMM)Pseudo Vec — (3DNow!)ANDNPS — Logical ANDC of Packed SPFP D = A (¬B)ANDNPD — Logical ANDC of Packed DPFPMin — MinimumPseudo VecN×8-Bit Integer MinimumN×16-Bit Integer MinimumN×SPFP Minimum1×SPFP Scalar Minimum2×DPFP Minimum1×DPFP Scalar MinimumMax — MaximumN×8-Bit Integer MaximumN×16-Bit Integer MaximumN×SPFP Maximum1×SPFP Scalar Maximum2×DPFP Maximum1×DPFP Scalar Maximum
10. Branching
Jump UnconditionallyJMP — JumpDelta JMPProtected Mode JMP (NEAR)Protected Mode JMP (FAR)Real Mode JMP (NEAR)Real Mode JMP (FAR)Delta JMPProtected Mode JMP (NEAR)Protected Mode JMP (FAR)Real Mode — NEAR or FAR has Same OpcodesProtected Mode — NEAR or FAR has Same OpcodesReal Mode — NEAR or FAR has Same OpcodesProtected Mode — NEAR or FAR has Same OpcodesJump ConditionallyJcc — BranchingDelta JMPBranch PredictionIntel Branch PredictionStatic Branch PredictionBack-Branch-TakenForward-Branch-Not-TakenBranching HintsAMD Branch PredictionBranch OptimizationPAUSE — (Spin Loop Hint)I-VU-QJECXZ/JCXZ — Jump if ECX/CX Is ZeroLOOPccLOOPPancake Memory LIFO QueueStackPUSH — Push Value onto StackPOP — Pop Value off StackPUSHA/PUSHAD — Push All General-Purpose RegistersPOPA/POPAD — Pop All General-Purpose RegistersPUSHFD/PUSHFQ and POPFD/POPFQENTER — Allocate Stack Frame for Procedure ARGSLEAVE — Deallocate Stack Frame of Procedure ARGSCALL Procedure (Function)CALLDelta CALLProtected Mode CALL (NEAR)Protected Mode CALL (FAR)Real Mode CALL (FAR)Protected Mode CALL (NEAR)Protected Mode CALL (FAR)Real Mode — NEAR or FAR has Same OpcodesProtected Mode — NEAR or FAR has Same OpcodesReal Mode — NEAR or FAR has Same OpcodesProtected Mode — NEAR or FAR has Same OpcodesRET/RETF — ReturnCalling Conventions (Stack Argument Methods)C Declaration (_CDECL)Standard Declaration (_STDCALL)Fast Call Declaration (_FASTCALL)Interrupt HandlingINT/INTO - Call Interrupt ProcedureIRET/IRETD/IRETQ — Interrupt ReturnCLI/STI — Clear (Reset)/Set Interrupt Flag
11. Branchless
Function y=ABS(x) 'Absolute' D = | A |Function y=MIN(p, q) 'Minimum'Function y=MAX(p, q) 'Maximum'Graphics 101 — Quick 2D Distance
12. Floating-Point Vector Addition and Subtraction
Floating-Point Vector Addition and SubtractionVector Floating-Point AdditionVector Floating-Point Addition with ScalarVector Floating-Point SubtractionVector Floating-Point Subtraction with ScalarVector Floating-Point Reverse SubtractionPseudo VecSingle-Precision Float AdditionSingle-Precision Float SubtractionSingle-Precision Vector Float AdditionSingle-Precision Vector Float SubtractionSingle-Precision Quad Vector Float AdditionSingle-Precision Quad Vector Float SubtractionPseudo Vec (×86)vmp_VecAdd (3DNow!)vmp_VecSub (3DNow!)vmp_QVecAdd (3DNow!)vmp_VecAdd (SSE) Unalignedvmp_VecAdd (SSE) Alignedvmp_QVecAdd (SSE) AlignedVector Scalar Addition and SubtractionSingle-Precision Quad Vector Float Scalar AdditionSingle-Precision Quad Vector Float Scalar SubtractionSpecial — FP Vector Addition and SubtractionVector Floating-Point Addition and SubtractionHADDPS/HADDPD/PFACC — Vector Floating-Point Horizontal AdditionHSUBPS/HSUBPD/PFNACC — Vector Floating-Point Horizontal SubtractionPFPNACC — Vector Floating-Point Horizontal Add/SubExercises
13. FP Vector Multiplication and Division
Floating-Point MultiplicationVector Floating-Point Multiplication(Semi-Vector) DPFP MultiplicationSPFP Scalar MultiplicationDPFP Scalar MultiplicationVector (Float) Multiplication — ADDPseudo VecSingle-Precision Float MultiplicationSingle-Precision Vector Float MultiplicationSingle-Precision Quad Vector Float MultiplicationSingle-Precision Quad Vector Float Multiplication-AddPseudo Vec (x86)vmp_VecMul (3DNow!)vmp_QVecMul (3DNow!)vmp_QVecMAdd (3DNow!)vmp_VecMul (SSE)vmp_VecMul (SSE) Alignedvmp_QVecMul (SSE) Alignedvmp_QVecMAdd (SSE) AlignedVector Scalar MultiplicationPseudo VecSingle-Precision Vector Float Multiplication with ScalarSingle-Precision Quad Vector Float Multiplication with ScalarPseudo Vec (x86)vmp_VecScale (3DNow!)vmp_VecScale (SSE) Alignedvmp_QVecScale (SSE) AlignedI-VU-QGraphics 101 — Dot ProductPseudo VecSingle-Precision Dot ProductPseudo Vec (x86)vmp_DotProduct (3DNow!)vmp_DotProduct (SSE) AlignedGraphics 101 — Cross Productvmp_CrossProduct (3DNow!)vmp_CrossProduct (SSE) AlignedVector Floating-Point Division(Vector) SPFP Division(Semi-Vector) DPFP DivisionSPFP Scalar DivisionDPFP Scalar DivisionN×SPFP Reciprocal1×SPFP Reciprocal (14-Bit)vmp_FDiv (3DNow!) Fast Float Division 14-Bit PrecisionSPFP Reciprocal (2 Stage) (24-Bit)vmp_FDiv (3DNow!) Standard Float Division 24-Bit Precisionvmp_FDiv (SSE) Standard Float Division 24-Bit PrecisionPseudo VecSingle-Precision Vector Float Scalar DivisionPseudo Vec (x86)vmp_QVecDiv (3DNow!) Fast Quad Float Division 14-Bit Precisionvmp_QVecDiv (3DNow!) Standard Quad Float Division 24-Bit Precisionvmp_QVecDiv (SSE) Standard Quad Float Division 24-Bit PrecisionExercises
14. Floating-Point Deux
SQRT — Square Root1×SPFP Scalar Square Root4×SPFP Square Root1×DPFP Scalar Square Root2×DPFP Square Root1×SPFP Scalar Reciprocal Square Root (15-Bit)Pseudo Vec(Float) Square RootPseudo Vec (x86)vmp_FSqrt (3DNow!) Fast Float 15-Bit PrecisionSPFP Square Root (2 Stage) (24-Bit)vmp_FSqrt (3DNow!) Standard Float 24-Bit Precisionvmp_FSqrt (SSE) Float Sqrt 24-Bit PrecisionVector Square RootPseudo VecVector Square RootQuad Vector Square RootPseudo Vec (x86)vmp_QVecSqrt (3DNow!) Fast Quad Float SQRT 15-Bit Precisionvmp_QVecSqrt (3DNow!) Quad Float Sqrt 24-Bit Precisionvmp_QVecSqrt (SSE) Float Sqrt 24-Bit Precisionvmp_QVecSqrtFast (SSE) Float Sqrt ApproximateGraphics 101 — Vector Magnitude (aka 3D Pythagorean Theorem)Pseudo VecPseudo Vec (x86)vmp_VecMagnitude (3DNow!)vmp_VecMagnitude (SSE) AlignedVector NormalizePseudo VecPseudo Vec (x86)vmp_VecNormalize (3DNow!)vmp_VecNormalize (SSE) Aligned
15. Binary-Coded Decimal (BCD)
BCDDAA — Decimal Adjust AL (After) AdditionDAS — Decimal Adjust AL (After) SubtractionAAA — ASCII Adjust (After) AdditionAAS — ASCII Adjust AL (After) SubtractionAAM — ASCII Adjust AX (After) MultiplicationAAD — ASCII Adjust AX (Before) DivisionFBLD — FPU (BCD Load)Graphics 101ASCII String to Double-Precision FloatASCII to Double
16. What CPUID?
CPUIDStandard CPUID EDX-Feature FlagsIntel — Standard CPUID ECX-Feature FlagsIntel — Extended #1 CPUID EDX-Feature FlagsAMD — Extended #1 CPUID EDX-Feature FlagsPIII Serial LicenseSample CPU Detection Codex86 CPU Detect — Bit Flagsx86 CPU Detect — VendorsCpu Detect — Information
17. PC I/O
IN — Input from PortVertical SyncOUT — Output to PortINSx — Input from Port to StringOUTSx — Output String to PortSerial/Parallel Port for IBM PCParallel PortParallel Port Dip SwitchesSerial Port
18. System
System "Lite"System Timing InstructionsRDPMC — Read Performance — Monitoring CountersRDTSC — Read Time-Stamp CounterCalculating Processor Speed80×86 ArchitectureCPU Status Registers (32-Bit EFLAGS/64-Bit RFLAGS)Protection RingsControl Registers(TPR) Task Priority Registers — (CR8)Debug RegistersCache ManipulationCache SizesCache Line SizesPREFETCHx — Prefetch Data into CachesLFENCE — Load FenceSFENCE — Store FenceMFENCE — Memory FenceCLFLUSH — Flush Cache LineINVD — Invalidate Cache (WO/Writeback)WBINVD — Write Back and Invalidate CacheSystem InstructionsARPL — Adjust Requested Privilege LevelBOUND — Check Array Index For Bounding ErrorCLTS — Clear Task Switch FlagHLT — Halt ProcessorUD2 — Undefined InstructionINVLPG — Invalidate TLBLAR — Load Access RightsLOCK — Assert Lock # Signal PrefixLSL — Load Segment LimitMOV — Move To/From Control RegistersMOV — Move To/From Debug RegistersSTMXCSR — Save MXCSR Register StateLDMXCSR — Load MXCSR Register StateSGDT/SIDT — Save Global/Interrupt Descriptor TableLGDT/LIDT — Load Global/Interrupt Descriptor TableSLDT — Save Local Descriptor TableLLDT — Load Local Descriptor TableSMSW — Save Machine Status WordLMSW — Load Machine Status WordSTR — Save Task RegisterLTR — Load Task RegisterRDMSR — Read from Model Specific RegisterWRMSR — Write to Model Specific RegisterSWAPGS — Swap GS Base RegisterSYSCALL — 64-Bit Fast System CallSYSRET — Fast Return from 64-Bit Fast System CallSYSENTER — Fast System CallSYSEXIT — Fast Return from Fast System CallRSM — Resume from System Management ModeVERR/VERW — Verify Segment for ReadingLDS/LES/LFS/LGS/LSS — Load Far PointerHyperthreading InstructionsMONITOR — MonitorMWAIT — Wait
19. Gfx 'R' Asm
Setting MemoryCopying MemorySpeed FreakGraphics 101 — Frame BufferGraphics 101 — BlitCopy BlitTransparent BlitGraphics 101 — Blit (MMX)Graphics Engine — Sprite LayeredGraphics Engine — Sprite OverlayGraphics 101 — Clipping Blit
20. MASM vs. NASM vs. TASM vs. WASM
MASM — Microsoft Macro AssemblerREPEATWHILEFORCompiler Intrinsics
21. Debugging Functions
Guidelines of Assembly DevelopmentVisual C++Tuning and OptimizationException Handling — AKA: Dang that 1.#QNANExceptionsHardware ExceptionSoftware ExceptionFPU Versus MMXPrint OutputFloat Array PrintVector PrintQuad Vector PrintQuaternion PrintMatrix PrintMemory DumpTest JigsMatrix Test FillMatrix Splat
22. Epilogue
A. Data Structure Definitions
B. Mnemonics
C. Reg/Mem Mapping
Glossary
References
ASE File FormatGame Development LinksMPEGSHA-1Personal Computer

Content preview from 32/64-Bit 80x86 Assembly Language Architecture

Chapter 15. Binary-Coded Decimal (BCD)

Converting an ASCII string to binary-coded decimal is as easy as pie (or is it a piece of cake?). In BCD, for every byte, the lower 4-bit nibble and upper 4-bit nibble each store a value from 0 to 9 (think double-digit hex only the upper six values A through F are ignored).

Workbench Files:\Bench\x86\chap15\project\platform

	project	platform
ASE to VMP	\ase2vmp\	\vc6
BCD 2^N	\bcd\	\vc.net

BCD

Table 15-1. ASCII numerical digit to hex and decimal values

ASCII	0	1	2	3	4	5	6	7	8	9
Hex	0x30	0x31	0x32	0x33	0x34	0x35	0x36	0x37	0x38	0x39
Decimal	48	49	50	51	52	53	54	55	56	57
BCD	0	1	2	3	4	5	6	7	8	9
Binary	0000	0001	0010	0011	0100	0101	0110	0111	1000	1001

Converting a BCD value from ASCII to a nibble is as easy as subtracting the hex value of 0x30, '0', or 48 decimal from the ASCII ...

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32/64-Bit 80x86 Assembly Language Architecture

by James Leiterman

Chapter 15. Binary-Coded Decimal (BCD)

BCD

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