1 Introduction1.1 The Advanced Encryption Standard (AES)1.2 FPGA1.3 HSTL (high-speed transceiver logic) IO standard2 Literature review3 Design methodology3.1 Simulation3.2 RTL analysis3.3 Synthesis3.4 Implementation3.5 Program and debug4 Results and analysis4.1 Computing total power consumption of HSTL_I_184.2 Computing total power consumption of HSTL_II4.3 Computing total power consumption of HSTL_II_185 Conclusion6 Future scope