All-Digital Frequency Synthesizer in Deep-Submicron CMOS

CHAPTER 4

ALL-DIGITAL PHASE-LOCKED LOOP

Digital-to-frequency conversion (DFC) of the normalized digitally controlled oscillator described in Chapter 3 operates in an open-loop manner. Consequently, its stability is quite poor, due to drift or wander of the self-generated phase and frequency. In this chapter we describe a phase correction mechanism by which the output phase, and hence frequency, is corrected periodically by comparison with a stable reference phase as established by the frequency reference (FREF) input of Fig. 1.1. In this way, the long-term frequency stability of the synthesizer matches that of the reference. The phase correction mechanism is performed entirely in the digital domain by phase-locking to the reference input the DCO clock generated. Design and building of its constituent blocks also follow the digital methodology.

Following the PLL classification in Best's widely cited book [33], the frequency synthesizer described in this chapter is not a classical digital PLL (DPLL), which actually is considered a semianalog circuit, but an all-digital PLL (ADPLL), with all building blocks defined as digital at the input/output level. It uses digital design and circuit techniques from the ground up. At the heart lies a digitally controlled oscillator (DCO), which deliberately avoids analog tuning voltage controls. The DCO is analogous to a flip-flop—the cornerstone of digital circuits—whose internals are analog, but the analog nature does not propagate beyond its ...