Architecture-Aware Optimization Strategies in Real-time Image Processing

5CDMS4HLS: A Novel Source-To-Source Compilation Strategy for HLS-Based FPGA Design

High-level synthesis (HLS) is one of the most recent synthesis techniques for FPGA-based designs. It can improve the performances of the designs, especially for real-time image/video processing developments. Nevertheless, in order to free the users from the complex coding rules and hardware constraints, an improved HLS design flow has emerged. This flow combines the source-to-source (S2S) compilers with HLS tools in order to automatically improve the efficiency of the source code. The motivation is to enable designers to concentrate their attention on the algorithm descriptions rather than hardware optimizations. Therefore, how to make compilers generate more efficient code for HLS becomes a new challenge. In this chapter, we present a novel HLS source transformation technic, Code and Directives Manipulation Strategy for HLS (CDMS4HLS), which optimizes the HLS source code in variant hierarchies by using different parallel computing strategies. We illustrate how this approach can effectively improve design performance and achieve more acceleration gains than the reference design flows.

5.1. S2S compiler-based HLS design framework

Figure 5.1(a) illustrates the framework of classical HLS-based FPGA designs. First of all, designers specify the software prototype of targeted algorithm in C-like languages and debug it in a test bench using common C compilers. Next, the confirmed code is imported into ...