STEREO DECODER CIRCUIT
The circuit diagram of decoder is shown in Fig. 22.5. The pilot tone is extracted from the multiplex input by means of a 19 kHz circuit immediately following the discriminator output. The pilot tone is then amplified by the first transistor and applied to the base of the second transistor. The second transistor is biased to operate in Class B; that is, only the positive half cycles of the amplified tone are amplified. The distorted waveform resulting from this type of amplification is very rich in second harmonic content, and this second harmonic (38 kHz) is extracted by means of a tuned circuit at the collector of the second transistor. The peak-to-peak amplitude of the 38 kHz signal, between the collector end of the coil ...
Get Consumer Electronics now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
