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Designing SOCs with Configured Cores by Steve Leibson

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8.8. System Design with the Diamond 212GP Processor Core

Figure 8.6 shows a system built with one Diamond 212GP controller core and three Diamond 108Mini processor cores. The 4-processor cores can communicate with each other and with global memory over the shared 32-bit PIF bus. A bus arbiter controls access to the PIF bus. This system closely resembles the system shown previously in Figure 7.5 but the Diamond 108Mini master processor in that system has been replaced by a Diamond 212GP processor in the system shown in Figure 8.6. The Diamond 212GP processor on the left of the figure is configured as the system master and the three Diamond 108Mini processor cores are slaves.

Figure 8.6. This multi-processor system design allows the master Diamond ...

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