Digital Logic Testing and Simulation, 2nd Edition

CONTENTS

Preface

1 Introduction

1.1 Introduction

1.2 Quality

1.3 The Test

1.4 The Design Process

1.5 Design Automation

1.6 Estimating Yield

1.7 Measuring Test Effectiveness

1.8 The Economics of Test

1.9 Case Studies

1.9.1 The Effectiveness of Fault Simulation

1.9.2 Evaluating Test Decisions

1.10 Summary

Problems

References

2 Simulation

2.1 Introduction

2.2 Background

2.3 The Simulation Hierarchy

2.4 The Logic Symbols

2.5 Sequential Circuit Behavior

2.6 The Compiled Simulator

2.6.1 Ternary Simulation

2.6.2 Sequential Circuit Simulation

2.6.3 Timing Considerations

2.6.4 Hazards

2.6.5 Hazard Detection

2.7 Event-Driven Simulation

2.7.1 Zero-Delay Simulation

2.7.2 Unit-Delay Simulation

2.7.3 Nominal-Delay Simulation

2.8 Multiple-Valued Simulation

2.9 Implementing the Nominal-Delay Simulator

2.9.1 The Scheduler

2.9.2 The Descriptor Cell

2.9.3 Evaluation Techniques

2.9.4 Race Detection in Nominal-Delay Simulation

2.9.5 Min–Max Timing

2.10 Switch-Level Simulation

2.11 Binary Decision Diagrams

2.11.1 Introduction

2.11.2 The Reduce Operation

2.11.3 The Apply Operation

2.12 Cycle Simulation

2.13 Timing Verification

2.13.1 Path Enumeration

2.13.2 Block-Oriented Analysis

2.14 Summary

Problems

References

3 Fault Simulation

3.1 Introduction

3.2 Approaches to Testing

3.3 Analysis of a Faulted Circuit

3.3.1 Analysis at the Component Level

3.3.2 Gate-Level Symbols

3.3.3 Analysis at the Gate Level ...