Digital System Clocking: High-Performance and Low-Power Aspects

CONTENTS

Preface

Chapter 1 Introduction

1.1 Clocking in Synchronous Systems

1.2 System Clock Design

1.2.1 Global System Clock Generation

1.2.2 On-Chip Clock Generation

1.2.3 Noise Sources and Loop Bandwidth

1.2.4 Design Considerations

1.3 Timing Parameters

1.3.1 Clock Skew

1.3.2 Clock Jitter

1.4 Clock Signal Distribution

1.4.1 Historical Overview

1.4.2 Clock Distribution in Modern Microprocessors

Chapter 2 Theory of Clocked Storage Elements

2.1 Latch-Based Clocked Storage Elements

2.1.1 True-Single-Phase-Clock Latch

2.1.2 Pulse Register Single Latch

2.2 Flip-Flop

2.2.1 Time Window-Based Flip-Flops

Chapter 3 Timing and Energy Parameters

3.1 Timing Parameters

3.1.1 Clock-to-Output Delay, tCQ

3.1.2 Setup Time, U

3.1.3 Hold Time, H

3.1.4 Late Data Arrival and Time Borrowing

3.1.5 Early Data Arrival and Internal Race Immunity

3.1.6 Minimum Data Pulse Width

3.2 Energy Parameters

3.2.1 Components of Energy Consumption

3.2.2 Energy Breakdown

3.2.3 Energy per Transition

3.2.4 Glitching Energy

3.3 Interface with Clock Network and Combinational Logic

3.3.1 Interface with Clock Network

3.3.2 Interface with Combinational Logic

Chapter 4 Pipelining and Timing Analysis

4.1 Analysis of a System that Uses a Flip-Flop

4.1.1 Late Data Arrival Analysis

4.1.2 Early Data Arrival Analysis

4.2 Analysis of a System that Uses a Single Latch

4.2.1 Late Data Arrival Analysis

4.2.2 Early Signal Arrival Analysis

4.3 Analysis of a System with a Two-Phase Clock and Two Latches in an M-S Arrangement

4.4 Analysis ...