This chapter deals with the timing and energy parameters of CSEs. We discuss the various definitions of timing parameters and provide insight into energy consumption in clocked storage elements.


Latches and flip-flops have different timing characteristics in general. However, it is possible to establish some common parameters for both. These parameters are based on timing relations between data and clock inputs that ensure correct circuit operation. We define basic timing parameters using a flip-flop and extend the analysis to a latch.

3.1.1. Clock-to-Output Delay, tcQ

The clock-to-output delay is the delay measured from the clock triggering edge to the output. It is a function of the arrival of data and clock signals, the slope of these signals, the supply voltage, temperature, process parameters, and the output load.

Basic timing diagrams of flip-flops are illustrated in Fig. 3.1. The flip-flop samples data, D, at the clock triggering edge (leading edge in this example) and generates the appropriate output after the propagation delay, tCQ,LH if output undergoes a 0–1 transition or tCQ,HL if output undergoes a 1–0 transition. The transitions occur between two consecutive clock edges, provided there is no violation of timing constraints between the data and clock inputs. Fundamental timing constraints between data and clock inputs are quantified with setup time, U, and hold time, H. Data have to be stable at least setup ...

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