This chapter presents clocked storage elements used in state-of-the-art microprocessors. MSLs, pulsed latches, and flip-flops represent the fundamental structures that are used as a baseline for derivation of circuits with extra features, such as internal clock gating, low-swing clock, or double-edge triggering. The design style and operation of each circuit implementation is discussed in detail. The chapter ends with a comparison, and general design and application recommendations of each circuit topology.


8.1.1. Derivation of Master-Slave Latch

Most commonly the MSL is built from two transmission-gate (TG) latches. There are several latch circuits that can be used in the implementation. The simplest one is the latch shown in Fig. 8.1a. The problem with this latch is that its storage node, S, appears dynamic because there is no pull-down transistor, which makes the latch susceptible to noise. A basic static version of this latch is shown in Fig. 8.1b, where a pull-down n-MOS device is added to the latch of Fig. 8.1a. The TG n-MOS transistor is a weak pull-up device, since a logic 1 has reduced swing, VDD - VTH. Also, there is a conflict between the TG n-MOS transistor and the feedback transistors during both pull-up and pull-down on the node S. These problems are remedied in the circuit shown in Fig. 8.1a. An extra TG in the feedback avoids the simultaneous pull-up/down problem, ...

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