6.1 Introduction6.2 Designing with HDLs6.3 Design Entry Methods6.4 Logic Synthesis6.5 Entities, Architectures, Packages, and Configurations6.6 A First Design6.7 Signals versus Variables6.8 Generics6.9 Reserved Words6.10 Data Types6.11 Concurrent versus Sequential Statements6.12 Loops and Program Control6.13 Coding Styles for VHDL6.14 Combinational Logic Design6.15 Sequential Logic Design6.16 Memories6.17 Unsigned versus Signed Arithmetic6.18 Testing the Design: The VHDL Test Bench6.19 File I/O for Test Bench Development