7.1. A Simplified Look at a Media Processing System7.1.1. Core Processing7.1.2. Input/Output Subsystems—Peripheral Interfaces7.1.2.1. Subsystem Control—Low-Speed Serial Interfaces7.1.2.2. Storage7.1.2.3. Connectivity7.1.2.4. Data Movement7.1.3. Memory Subsystem7.2. System Resource Partitioning and Code Optimization7.3. Event Generation and Handling7.3.1. System Interrupts7.4. Programming Methodology7.5. Architectural Features for Efficient Programming7.5.1. Multiple Operations per Cycle7.5.2. Hardware Loop Constructs7.5.3. Specialized Addressing Modes7.5.3.1. Byte Addressability7.5.3.2. Circular Buffering7.5.3.3. Bit Reversal7.5.4. Interlocked Instruction Pipelines7.6. Compiler Considerations for Efficient Programming7.6.1. Choosing Data Types7.6.1.1. Arrays versus Pointers7.6.1.2. Division7.6.1.3. Loops7.6.1.4. Data Buffers7.6.1.5. Intrinsics and In-lining7.6.1.6. Volatile Data7.7. System and Core Synchronization7.7.1. Load/Store Synchronization7.7.2. Ordering7.7.3. Atomic Operations7.8. Memory Architecture—the Need for Management7.8.1. Memory Access Trade-offs7.8.2. Instruction Memory Management—to Cache or to DMA?7.8.3. Data Memory Management7.8.3.1. What about Data Cache?7.8.4. System Guidelines for Choosing between DMA and Cache7.8.4.1. Instruction Cache, Data DMA7.8.4.2. Instruction Cache, Data DMA/Cache7.8.4.3. Instruction DMA, Data DMA7.8.5. Memory Management Unit (MMU)7.8.5.1. CPLB Management7.8.5.2. Memory Translation7.9. Physics of Data Movement7.9.1. Grouping Like Transfers to Minimize Memory Bus Turnarounds7.9.2. Understanding Core and DMA SDRAM Accesses7.9.3. Keeping SDRAM Rows Open and Performing Multiple Passes on Data7.9.4. Optimizing the System Clock Settings and Ensuring Refresh Rates Are Tuned for the Speed at Which SDRAM Runs7.9.5. Exploiting Priority and Arbitration Schemes between System Resources7.10. Media Processing Frameworks7.10.1. What Is a Framework?7.11. Defining Your Framework7.11.1. The Application Timeline7.11.1.1. Evaluating BandwidthProcessor BandwidthDMA BandwidthMemory Bandwidth7.12. Asymmetric and Symmetric Dual-Core Processors7.13. Programming Models7.13.1. Asymmetric Programming Model7.13.2. Homogeneous Programming Model7.13.2.1. Master-Slave Programming Model7.13.2.2. Pipelined Programming Model7.14. Strategies for Architecting a Framework7.14.1. Processing Data On-the-Fly7.14.2. Programming Ease Trumps Performance7.14.3. Performance-based Framework7.14.3.1. Image Pipe and Compression Example7.14.3.2. High Performance Decoder Example7.14.4. Framework Tips7.15. Other Topics in Media Frameworks7.15.1. Audio-Video Synchronization7.15.2. Managing System Flow7.15.3. Frameworks and Algorithm Complexity