Embedded SoPC Design with Nios II Processor and Verilog Examples

CHAPTER 14

CUSTOM I/O PERIPHERAL WITH PIO CORES

The Altera SOPC platform includes a sophisticated structure to create custom I/O interfaces to integrate I/O peripherals into Nios II systems. The process is somewhat tedious. For an I/O peripheral with just a few ports and simple timing requirement, it is possible to utilize multiple PIO cores to function as I/O buffers rather than creating a new core. In this chapter, we demonstrate this scheme by interfacing the previous division circuit with a Nios II processor.

14.1 INTRODUCTION

A Nios II processor utilizes a memory-mapped I/O scheme to access I/O peripherals. The simplest interface between a processor and an I/O peripheral is a collection of registers. The processor treats these registers as memory locations and reads and writes data accordingly. For example, the JTAG UART core in Section 11.3 contains two interface registers and the timer core in Section 11.4 contains six interface registers. Altera SOPC platform includes a sophisticated structure, known as Avalon interconnect, to create custom I/O interfaces to accommodate the buffering and timing requirements of I/O peripherals and hardware accelerators. The Avalon interconnect is discussed and used in the remaining chapters of Part III and the chapters of Part IV.

Creating a new IP core in the SOPC platform is a somewhat tedious procedure. An alternative is to utilize the existing PIO cores as interface registers and instantiate a PIO module for each I/O port. Since each ...