Multiplier designs are a simple way of studying different varieties of digital logic designs. It is possible to develop different multiplier examples to study the varieties of design approaches and implement these designs using FPGAs. In the following sections Xilinx 3000 implementations are assumed, but the approaches vary from fully automated to handcrafted with corresponding gains in performance.
The simplest of the multiplier designs is a parallel-combinational logic multiplier. This multiplier produces a result by adding the partial products of equal binary weight with the carries of the lower binary weight. The design consists simply of AND, OR, XOR, and inverter gates at the top-level schematic.
Schematic Entry Figure 5-31 is an example of a 4- × 4-bit combinational logic multiplier. The design was created using ViewLogic WorkView. Using CAD tools, a logic design can be entered directly as a top-level schematic, manually connecting gates together. To obtain more information about creating a schematic design, refer to the current Xilinx and/or Viewlogic WorkView manuals.
Functional Simulation It is always a good idea to check the design functionality before actually continuing with the creation of the layout file. The software used to create the schematic design provided support for a functional simulation of the schematic circuit. Refer to Figure 5–32.