Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

5.7   A PARALLEL CONTROLLER DESIGN*

An outline of the design and implementation of a video framestore design is presented that used the Petri net method described in Chapter 2, and is implemented on a Xilinx LCA.

The function of the framestore is to receive or transmit digital video data from a memory in a raster scan format. Region of interest (ROI) is supported, allowing the reception and transmission of frames of any size. Video data arrive on a 16-bit-wide bus every 100 ns. A frame synchronization signal defines the start of a field of data of 260 lines by 760 pixels. Each line starts with a horizontal synchronization signal. The video controller has to deposit the data in a video framestore in the correct order (interleaving two fields to create a full frame) and to manage accesses to the memory. A second independent video channel operates at the same time, but it must access a different block of memory. A transputer is able to access both memory blocks while video operations are being performed. At the end of a frame, the video channels may be required to switch memory banks, and this must be handled by the controller.

Figure 5–33. XACT view of the parallel multiplier.

The controller has a number of registers containing its operating parameters, such as horizontal start and end count, vertical start and end count, and start address in memory. Figure 5–36 shows the datapath ...