Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

3.8   HISTORICAL BACKGROUND

3.8.1   Early Work

The origins of much of today's FPGA research are in work in the late 1960s and early 1970s on cellular arrays. This work was mainly concerned with improving the fault tolerance of logic structures, thus allowing larger silicon areas or whole wafers to be used to implement logic. The method proposed was to cover the wafer with a regular array of restructurable cells capable of implementing general logic functions. Both fuse- and flip-flop-programmed structures were proposed and investigated. Important early work in this area was done by Manning [Mann77], Minnick [Minn64], Wahlstrom [Wahl67], and Shoup [Shoup70]. A good survey article of the early research appears in [Minn67].

3.8.2   PALs and Structured PALs

The first programmable two-level logic products were PROMs from Harris and Monolithic Memories. Monolithic Memories later introduced field-programmable logic-array (FPLA) devices based on bipolar fusible link technology, and later Birkner and Chua at Monolithic Memories invented the PAL architecture that was to dominate the marketplace, replacing TTL as the method of choice for implementing glue-logic functions.

The PAL concept was further improved with the introduction of GAL devices. These devices were erasable either electrically or by UV light and used low power CMOS rather than bipolar technology. The most popular of these devices, the 22V10 can emulate a wide variety of conventional PALs.

Structured PALs were introduced and ...