Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems

4.6   PLACEMENT, ROUTING, AND WIREABILITY

An eternal requirement in CAD tool provision is for automatic place and route, preferably with 100% guaranteed success and with a short run time. Unfortunately, placement and routing takes place within the context of a real design and physical reality imposed by one or more FPGAs, the implementation medium. Any design contains a demand for wires with its point-to-point connections and bus structures. Since the FPGA contains a finite number of wires, all FPGA architectures have a defined wiring capacity. When there are gross discrepancies between the wiring demand of a particular design and the wiring capacity of the target FPGA, it is likely to be difficult to discover an implementation by any method including advanced placement and routing algorithms. It is worth trying to understand the relationship between wiring capacity and demand so that better engineering decisions can be made about the suitability of a particular FPGA for a particular design.

Figure 4–22. Physical designs for the display driver: manual CAL design.

4.6.1   Rent’s Rule and Package Pin-outs

Rent’s rule was originally “discovered" from examining packages of logic modules [Russo71]. It attempts to answer the question, “How many connections (n) are required to a structure holding a number of components (N) each of which has a number of connections (m)?” (see Figure 4–24 ...