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Formal Verification

Book Description

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.

  • Learn formal verification algorithms to gain full coverage without exhaustive simulation
  • Understand formal verification tools and how they differ from simulation tools
  • Create instant test benches to gain insight into how models work and find initial bugs
  • Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Foreword for “Formal Verification: An Essential Toolkit for Modern VLSI Design”
  6. Acknowledgments
  7. Chapter 1. Formal verification: From dreams to reality
    1. What is FV?
    2. Why This Book?
    3. A Motivating Anecdote
    4. FV: The Next Level of Depth
    5. The Emergence of Practical FV
    6. Challenges in Implementing FV
    7. Amplifying the Power of Formal
    8. Getting the Most Out of This Book
    9. Practical Tips from This Chapter
    10. Further Reading
  8. Chapter 2. Basic formal verification algorithms
    1. Formal Verification (FV) in the Validation Process
    2. Comparing Specifications
    3. Formalizing Operation Definitions
    4. Boolean Algebra Notation
    5. BDDs
    6. Boolean Satisfiability
    7. Chapter Summary
    8. Further Reading
  9. Chapter 3. Introduction to systemverilog assertions
    1. Basic Assertion Concepts
    2. Immediate Assertions
    3. Sequences, Properties, and Concurrent Assertions
    4. Summary
    5. Further Reading
  10. Chapter 4. Formal property verification
    1. What is FPV?
    2. Example for this Chapter: Combination Lock
    3. Bringing Up a Basic FPV Environment
    4. How is FPV Different from Simulation?
    5. Summary
    6. Further Reading
  11. Chapter 5. Effective FPV for design exercise
    1. Example for This Chapter: Traffic Light Controller
    2. Creating a Design Exercise Plan
    3. Setting Up the Design Exercise FPV Environment
    4. Wiggling the Design
    5. Exploring More Interesting Behaviors
    6. Removing Simplifications and Exploring More Behaviors
    7. Summary
    8. Further Reading
  12. Chapter 6. Effective FPV for verification
    1. Deciding on Your FPV Goals
    2. Staging Your FPV Efforts
    3. Example for this Chapter: Simple ALU
    4. Understanding the Design
    5. Creating the FPV Verification Plan
    6. Removing Simplifications and Exploring More Behaviors
    7. Summary
    8. Further Reading
  13. Chapter 7. FPV “Apps” for specific SOC problems
    1. Reusable Protocol Verification
    2. Unreachable Coverage Elimination
    3. Connectivity Verification
    4. Control Register Verification
    5. Post-Silicon Debug
    6. Summary
    7. Further Reading
  14. Chapter 8. Formal equivalence verification
    1. Types of Equivalence to Check
    2. FEV Use Cases
    3. Running FEV
    4. Additional FEV Challenges
    5. Summary
    6. Further Reading
  15. Chapter 9. Formal verification’s greatest bloopers: The danger of false positives
    1. Misuse of the SVA Language
    2. Vacuity Issues
    3. Implicit or Unstated Assumptions
    4. Division of Labor
    5. Summary
    6. Further Reading
  16. Chapter 10. Dealing with complexity
    1. Design State and Associated Complexity
    2. Example for this Chapter: Memory Controller
    3. Observing Complexity Issues
    4. Simple Techniques for Convergence
    5. Helper Assumptions … and Not-So-Helpful Assumptions
    6. Generalizing Analysis Using Free Variables
    7. Abstraction Models for Complexity Reduction
    8. Summary
    9. Further Reading
  17. Chapter 11. Your new FV-aware lifestyle
    1. Uses of FV
    2. Getting Started
    3. Making Your Manager Happy
    4. What Do FVers Really Do?
    5. Summary
    6. Further Reading
  18. Index