The IRIS Behavioural Synthesis Tool

The descriptions in Chapter 7 have highlighted the range of tools and methodologies available for implementing FPGA-based DSP systems. In particular, the chapter highlighted the tools for synthesizing dedicated IP cores; however, the discussion in Chapter 8 highlighted some of the issues in creating the circuit architectures that are the basis of these IP cores. The exploration of the algorithmic concurrency in the form of levels of parallelism and pipelining in the algorithm representation typically a DFG, is instrumental in generating an efficient FPGA implementation. A number of simple examples were covered to illustrate the basic techniques, but the reality is that these techniques are difficult to explore on even reasonably complex algorithms. For this reason, there is a strong interest in developing synthesis tools to automate many of these techniques.

Behavioural synthesis tools accept a behavioural description of the functionality required of the hardware, then select suitable hardware building block components from libraries supplied by the tool vendor or the user, generate the interconnections needed among components, assign operations and data used in the behavioural description to the selected computational and storage components, determine the order in which operations execute on computational and storage components, and then generate a specification for a controller to implement this sequencing of operations. The resulting design ...

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