FPGA Hardware-Entwurf, 4th Edition

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Tabelle 4.16: Beispieloperation im 3-Bit-Addierer aus Listing 4.18

Abb. 4.39: Syntheseergebnis 3-Bit-Addierer.

4.4.3Implementierung von Subtrahierern in FPGAs

Die Implementierung der Subtraktion $a - b$ wird besonders einfach, wenn man sie auf die Addition $a + (- b)$ zurückführt [40, 81]. Die negative Dualzahl $- b$ wird dabei im so genannten „Zweier-Komplement“ dargestellt. Der (dezimale) Wert einer Dualzahl $b$

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