Hardware Design Verification: Simulation and Formal Method-Based Approaches

Chapter 5. Test Scenarios, Assertions, and Coverage

Chapter Highlights

• Hierarchical verification

• Test plan

• Pseudorandom test generator

• Assertions

• SystemVerilog assertion

• Verification coverage

In the previous chapters we discussed the static removal of design errors, structure and use of simulators, and test bench creation. With these components in place, we are ready to simulate designs. The challenge in simulation is to uncover as many bugs as possible within a realistic time frame. To uncover all bugs, one can exhaustively enumerate all possible input patterns and internal states. However, this is seldom feasible in practice. In the following discussion, we will compute an upper bound on the number of input patterns to test exhaustively a sequential ...