High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting

Chapter 10. Clock Models in Link BER Analysis

Sam Chang, Jihong Ren, and Dan Oh

Jitter, associated with the clocking circuitry, is one of the largest timing error components in high-speed links. Clock jitter is generated by clock generation (PLL) circuits, and clock distribution (buffers) circuits. The dominant source of clock jitter is power supply noise (see Chapter 14, “Supply Noise and Jitter Characterization” and Chapter 2, “High-Speed Signaling Basics” Section 2.2.5). Because the jitter induced by power supply noise is strongly colored due to the frequency-dependent supply impedance profile and circuit sensitivity, modeling the frequency content of this jitter is crucial, in order to determine accurate channel margin. Traditionally clock ...