September 2013
Intermediate to advanced
232 pages
7h 30m
English
book
Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers
by Rezaur Rahman
Content preview from Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers
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CHAPTER 5
Xeon Phi Cache and Memory Subsystem
The preceding chapter showed how the Intel Xeon Phi coprocessor uses a two-dimensional tiled architecture approach to designing manycore coprocessors. In this architecture, the cores are replicated on die and connected through on-die wire interconnects. The network connecting the various functional units is a critical piece that may become a bottleneck as more cores and devices are added to the network in a chip multiprocessor (CMP) design such as Intel Xeon Phi uses. The interconnect design choices are primarily determined by the number of cores, expected interconnect performance, chip area limitation, ...
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